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Explorer
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Registered: ‎10-09-2018

unroutable placement - 2 aurora & 1 PCIe

Hello,

System- Artix 7 ( xc7a100t-2fgg484), Win10-64 bit, ISE 14.7

 

I am having 2 Aurora GTP and 1 PCIe core in same Quad in above chipset. I have merged my design into 1 GTPE2_common which is present into PCIe and output of pll1 is going to both aurora(same freq) gtpe2_channel.

So PCIe "gtpe2_common" has 2 output-> 1st output going to PCIe "gtpe2_channel" and 2nd output going to both aurora's "gtpe2_channel".

 

I am getting following error

 

 

 

ERROR:Place:1388 - Unroutable Placement! A BUFDS / GT clock component pair have
   been found that are not placed at a routable BUFDS / GT site pair. The BUFDS
   component <pcie_inst/refclk_ibuf> is placed at site <IBUFDS_GTE2_X0Y3>. The
   GT component
   <pcie_inst/pcie_i/gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_quad.pipe_common.
   qpll_wrapper_i/gtp_common.gtpe2_common_i> is placed at site
   <GTPE2_COMMON_X0Y1>. The GT is driven by this BUFDS in regular mode and they
   must be placed in the same clock region to be routable because the BUFDS
   connects to the GT on a GTREFCLK pin. Furthermore, depending on the GTREFCLK
   bit used, only some BUFDS sites in the same clock region are routable to it.
   Check usage documents for routability of the device. This placement is
   UNROUTABLE in PAR and therefore, this error condition should be fixed in your
   design. You may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to
   demote this message to a WARNING in order to generate an NCD file. This NCD
   file can then be used in FPGA Editor to debug the problem. A list of all the
   COMP.PINS used in this clock placement rule is listed below. These examples
   can be used directly in the .ucf file to demote this ERROR to a WARNING.
   < PIN "pcie_inst/refclk_ibuf.O" CLOCK_DEDICATED_ROUTE = FALSE; >
   < PIN
   "pcie_inst/pcie_i/gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_quad.pipe_common.
   qpll_wrapper_i/gtp_common.gtpe2_common_i.GTREFCLK0" CLOCK_DEDICATED_ROUTE =
   FALSE; >

ERROR:Place:1388 - Unroutable Placement! A BUFDS / GT clock component pair have
   been found that are not placed at a routable BUFDS / GT site pair. The BUFDS
   component <aurora1_exdes_inst/IBUFDS_GTE2_CLK1> is placed at site
   <IBUFDS_GTE2_X0Y2>. The GT component
   <pcie_inst/pcie_i/gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_quad.pipe_common.
   qpll_wrapper_i/gtp_common.gtpe2_common_i> is placed at site
   <GTPE2_COMMON_X0Y1>. The GT is driven by this BUFDS in regular mode and they
   must be placed in the same clock region to be routable because the BUFDS
   connects to the GT on a GTREFCLK pin. Furthermore, depending on the GTREFCLK
   bit used, only some BUFDS sites in the same clock region are routable to it.
   Check usage documents for routability of the device. This placement is
   UNROUTABLE in PAR and therefore, this error condition should be fixed in your
   design. You may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to
   demote this message to a WARNING in order to generate an NCD file. This NCD
   file can then be used in FPGA Editor to debug the problem. A list of all the
   COMP.PINS used in this clock placement rule is listed below. These examples
   can be used directly in the .ucf file to demote this ERROR to a WARNING.
   < PIN "aurora1_exdes_inst/IBUFDS_GTE2_CLK1.O" CLOCK_DEDICATED_ROUTE = FALSE;
   >
   < PIN
   "pcie_inst/pcie_i/gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_quad.pipe_common.
   qpll_wrapper_i/gtp_common.gtpe2_common_i.GTREFCLK1" CLOCK_DEDICATED_ROUTE =
   FALSE; >

Phase 4.2  Initial Placement for Architecture Specific Features
(Checksum:5db3ceb6) REAL time: 27 secs 

Total REAL time to Placer completion: 27 secs 
Total CPU  time to Placer completion: 27 secs 
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

 

 

 

 

I have tried interchanging LOC constraints of both CLK.

I have attached ucf, ncd, pcf file here. Please let me know what I am doing wrong.

 

Thank You!

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8 Replies
Moderator
Moderator
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Registered: ‎07-30-2007

Your design has multiple interfaces instantiating an input buffer for the refclk.  If they are sharing a refclk they the loc's of this instantiation will clash - they will try to instantiate the same IBUFDS_GTE* more than once.  You must remove the the refclk input buffer from one of the designs and drive the lines that it was driving with the output of the refclk buffer from the other wizard design.  




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Explorer
Explorer
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Registered: ‎10-09-2018

Hello @roym ,

I am merging 3 IP's into single quad. 2 aurora IP's and 1 PCIe IP are merging together with 1 gtpe2_common.

I am using PCIe gtpe2_common,so i have commented other two generated with core.

PCIe is using PLL0  to drive its channel ,So PLL1 I am utilizing for both Aurora IP which are using same frequency( I have changed the attributes for PLL1 in gtpe2_common and connected its output port to aurora gtpe2_channel port as it required).

Now I have to give 2 different input clk to pll ,So I can get two clk for PCIe and Aurora, that means I have to use 2 ibufds_gte2. So how can I remove refclk ip buffer ,as you said above?

Am i missing anything here?

Thanks!

Avinash 

 

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Moderator
Moderator
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Registered: ‎07-30-2007

I am not clear on what you want.  The thing is there is only one input buffer per refclk pin.  You can't assign 2 input buffers to one pin or the instantiations will clash.  This appears to be the error message you have.  One input buffer can potentially drive both channels.  




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Explorer
Explorer
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Registered: ‎10-09-2018

Hello @roym ,

I want to use 2 refclk for two PLL. 

refclk0 will go to input PLL0 in gtpe2_common in pcie core & refclk1 will go to input PLL1 in gtpe2_common of same pcie core. Hence I'll need 2 ibufds_gte2.

I am giving Aurora clk to 1st ibufds_gte2 and output of that is going to PLL1 as said above. PCIe clk is driving 2nd ibufds_gte2 and output of that is going to PLL0 in gtpe2_common as said above. 

and then output of pll1 is driving gtpe2_channel in Aurora core.

 

This is what I am trying to do. Am I doing it right?

 

Thanks!

Avinash

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Moderator
Moderator
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Registered: ‎07-30-2007

It is apparently saying you are routing a refclk from a quad or pin too far away.  Reference clock pins are dedicated so there are only a couple of viable pins you can use.  I can't see what you've chosen as my utilities are saying your *.rar file is corrupt?




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Explorer
Explorer
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Registered: ‎10-09-2018

Hello @roym ,

I have used below pins:

gtp channelgtp channelaurora constraintsaurora constraintsPCIe constraintsPCIe constraints

this should not make any problem,right?

--

I have one more question. 

I am using two pll for two different frequency, that means 2 tx & 2 rx of Aurora will work on PLL1 frequency and 1 tx & 1 rx of PCIe will work on pll0 frequency.

So all TX or RX of these 3 gtp_channel are not working on same frequency. Is that possible?

 

Thanks!

Avinash

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Moderator
Moderator
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Registered: ‎07-30-2007

Check the sys_clk_p/n connections.  Usually a pin with this name is going to drive a regular input buffer and then a BUFG.  If you have repurposed this into a refclk/ system clock combination you must remove the BUFG and regular clock input buffer and use only the refclk buffer.  The odiv2 can drive a bufg_gt which can drive anything a regular bufg can drive.

In addition you have three designs that will all instatiate a gtpe*_common.  Two of the commons have to be removed and one has to drive all three designs.  Are you doing this as well?




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Explorer
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Registered: ‎10-09-2018

Hello @roym ,

 

Sys_clk_p/n is going to IBUFDS_GTE2 and output of that going to pll0 in pcie gtpe2_common. So now I don't need to remove anything right?

Yes, I have removed 2 gtpe2_common from 2 aurora and only 1 common in PCIe is working.

-- 

please give me answer of last question, Can I use 2 different freq clk for TX & RX in different gtpe2_channel for aurora and PCIe?

You can refer this question in my above reply.

I have attached my whole project here, please give a look. -----------     I have done in ISE 14.7

Thanks!

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