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Visitor rolsfenix
Visitor
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Registered: ‎05-15-2018

wizard gtrefclkxx_in more than one quad enabled

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I'm using the GTY wizard on a VU3P design. Up until now I've used all 4 transceivers in one single quad and the wizard generates gtrefclk00_in and gtrefclk01_in each 1 bit wide, which makes sense. In this case I'm using both QPLLs with the same MGTREF input in the quad. This works fine. 

I then tried a design which enabled the transceivers in *TWO* adjacent quads for a total of 8 transceivers. In this case the quads were 128 and 127, in the wizard 128 is shown 'above' 127. The gtrefclk0x_in are now TWO bits wide, one for each COMMON, however there's no obvious way to tell which is which, are they in quad number order so gtrefclkxx_in[0] is quad 127, or north-south order in which case it's 128? 

Finally, I really actually want to use one single MGTREF input, so I set quad 128 QPLL inputs to MGTREFCLK0 and quad 127 QPLL inputs to MGTREFCLK0 of the quad above, 128. The gtwizard diagram correctly shows all QPLLs driven from the same MGTREF pins, however the wizard STILL generates gtrefclkxx_in with 2 bits, even thought there's only now one single clock input to the two quads. Nor do the gtsouthrefclk or gtnorthrefclk inputs become enabled, I thought perhaps I'd have to connect to those, 

In this instance, with quad 128 QPLLs driven off quad 128 MGTREFCLK inputs and quad 127 QPLL driven off the MGTREFCLK inputs from the quad above (128), what am I supposed to connect to gtrefclkxx_in[0.1], in which order and do I need to enable the gtsouthrefclkxx_in inputs in order to get the routing correct.  

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Visitor rolsfenix
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166 Views
Registered: ‎05-15-2018

Re: wizard gtrefclkxx_in more than one quad enabled

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And it seems that it does work. The synthesis looks strange as both COMMONs are set up as if they were sourcing from their own quad refclock, however there's two, very easy-to-miss, lines in the implementation

INFO: [Route 35-467] Router swapped GT pin i_eth_1g/i_gtwizard_inst/inst/gen_gtwizard_gtye4_top.gtwizard_1g_top_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_common.gen_common_container[3].gen_enabled_common.gtye4_common_wrapper_inst/common_inst/gtye4_common_gen.GTYE4_COMMON_PRIM_INST/GTREFCLK00 to physical pin GTYE4_COMMON_X0Y3/COM0_REFCLKOUT5
INFO: [Route 35-467] Router swapped GT pin i_eth_1g/i_gtwizard_inst/inst/gen_gtwizard_gtye4_top.gtwizard_1g_top_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_common.gen_common_container[3].gen_enabled_common.gtye4_common_wrapper_inst/common_inst/gtye4_common_gen.GTYE4_COMMON_PRIM_INST/GTREFCLK01 to physical pin GTYE4_COMMON_X0Y3/COM2_REFCLKOUT5

which I believe are the router fixing those clock networks to come from the other quad. 

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Re: wizard gtrefclkxx_in more than one quad enabled

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Hello @rolsfenix 

Did you set the GUI setting as follow ?
GTY_VU3P_CLK.png

then gtrefclk00_in[1:0] is expected result.
Just connect this signal to a single IBUFDS_GTE4 and assign the IO placement correctly.

GTY_one_refclk_pin.png

Thanks & regards
Leo

Visitor rolsfenix
Visitor
233 Views
Registered: ‎05-15-2018

Re: wizard gtrefclkxx_in more than one quad enabled

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Yes that picture is exactly how I set it up. So I just repeat the buffered clock signal to both gtrefclk00_in[1:0], ie it would look like this

wire buffered_refclk; // assume that's been correctly assigned to the IBUFDS_GTE4 output

.....

      .gtrefclk00_in( { buffered_refclk, buffered_refclk } )

if that's correct, that's easy thanks. 

 

Xilinx Employee
Xilinx Employee
230 Views
Registered: ‎03-30-2016

Re: wizard gtrefclkxx_in more than one quad enabled

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Hello @rolsfenix 

Then it should work.
Please try to implement your design.

Regards
Leo

Visitor rolsfenix
Visitor
167 Views
Registered: ‎05-15-2018

Re: wizard gtrefclkxx_in more than one quad enabled

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And it seems that it does work. The synthesis looks strange as both COMMONs are set up as if they were sourcing from their own quad refclock, however there's two, very easy-to-miss, lines in the implementation

INFO: [Route 35-467] Router swapped GT pin i_eth_1g/i_gtwizard_inst/inst/gen_gtwizard_gtye4_top.gtwizard_1g_top_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_common.gen_common_container[3].gen_enabled_common.gtye4_common_wrapper_inst/common_inst/gtye4_common_gen.GTYE4_COMMON_PRIM_INST/GTREFCLK00 to physical pin GTYE4_COMMON_X0Y3/COM0_REFCLKOUT5
INFO: [Route 35-467] Router swapped GT pin i_eth_1g/i_gtwizard_inst/inst/gen_gtwizard_gtye4_top.gtwizard_1g_top_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_common.gen_common_container[3].gen_enabled_common.gtye4_common_wrapper_inst/common_inst/gtye4_common_gen.GTYE4_COMMON_PRIM_INST/GTREFCLK01 to physical pin GTYE4_COMMON_X0Y3/COM2_REFCLKOUT5

which I believe are the router fixing those clock networks to come from the other quad. 

View solution in original post

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