cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
liuyue123
Participant
Participant
606 Views
Registered: ‎11-26-2018

zynq7045 srio 8b10b error

hellow,we have a zynq7045 design with PCIE SRIO AURORA in it.But only the pcie can work at gen2(5Gbps),the SRIO and aurora can only work at 1.25Gbps.We loopback the gtx port on board,and test the ports with IBERT,the result shows the ports can work at 10Gbps with IBERT,but the AURORA and SRIO only can work at 1.25Gbps even in loopback mode.

the log reads there is 8B10B error while we use the SRIO,and we have no ideas aboult this problem .

the link seems ok,but the SRIO and AURORA can't work well,we have test these IP core on the board of previous version,it works well,but on this version ,it can't.

0 Kudos
7 Replies
roym
Moderator
Moderator
546 Views
Registered: ‎07-30-2007

If it works on the boards previous version you need to look hard at any changes you have made to the board.  Look and make sure the power supplies for the GT's are not sagging when you get the full design loaded.  Has the board maintained signal integrity on these lines- no new stubs tht might be causing reflections. (Your description of the IBERT test makes me unsure of whether it tested the board traces).  Scope your refclk too to make sure it is clean and there is nothing interferring with it. 

Some 8B/10B errors are probably indicating that the board is having trouble keeping the comma locked. 




----------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution
Be sure to visit the Resources post periodically to keep up with the latest
https://forums.xilinx.com/t5/Serial-Transceivers/Serial-Transceiver-Forum-Guidelines-and-Useful-Resources/td-p/1173590
----------------------------------------------------------------------------


drjohnsmith
Teacher
Teacher
540 Views
Registered: ‎07-09-2009

try the same cables, test equipment etc on the old board just to rule them out
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
liuyue123
Participant
Participant
502 Views
Registered: ‎11-26-2018

we have checked,but found nothing important.the GT's trace of the layout has nothing changed,and the DC and AC of the power is OK. We test the AURORA with the pcie refclk(from the host device clk line),it seems ok at 5Gbps,it might be that there is something wrong with the oscillator of the refclk ,or the configuration of GT's clk pin is different from PCIE to the others .The layout of clk has no change from pervious version.
0 Kudos
liuyue123
Participant
Participant
500 Views
Registered: ‎11-26-2018

we have checked,but found nothing important.the GT's trace of the layout has nothing changed,and the DC and AC of the power is OK. We test the AURORA with the pcie refclk(from the host device clk line),it seems ok at 5Gbps,it might be that there is something wrong with the oscillator of the refclk ,or the configuration of GT's clk pin is different from PCIE to the others .The layout of clk has no change from pervious version.

0 Kudos
liuyue123
Participant
Participant
497 Views
Registered: ‎11-26-2018

There's nothing I can do,I apply for a wideband oscilloscope ,we will do some hardware test the day after tomorrow

0 Kudos
drjohnsmith
Teacher
Teacher
451 Views
Registered: ‎07-09-2009

Its unlikely , but be aware,
not all pcb manufacturers are as consistent as they should be.

Over the decades I've had layers missed, extra layers duplicated , wrong stack up of board, wrong board type .

Could be that first boards were wrong, but worked whilst the new ones are right and fail,
Or it could be that your design is marginal, and it happens on on batch it ran, on next fails, Different board, different batch of chips etc

If it can go wrong it will at some time,

 

BTW:

are you up to spped on these

https://www.xilinx.com/support/documentation/application_notes/xapp1322-transceiver-link-tuning.pdf

CH6

https://www.xilinx.com/Attachment/Hardware_Debug_Best_Practices.pdf

 

The tools have great ways built in to allow eye diagrams to be looked at

    suggest you d that for the old and new boards

 

 

My beting is its cables ,loose connections , or finger trouble,

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
liuyue123
Participant
Participant
439 Views
Registered: ‎11-26-2018

thanks for your suggestions,I'll try these means. The phenomenon is so weird,we can't find the reason ,the IBERT is ok at 10Gbps,while the SRIO and AURORA fail at 2.5Gbps,the link between T and R seems ok,but the ip core work incorrectly.And the same IP worked well on the previous board.

 

0 Kudos