cancel
Showing results for
Show  only  | Search instead for
Did you mean:
Highlighted
Explorer
11,942 Views
Registered: ‎05-15-2009

## Impedance of IO line?

Hi,

I'm assigning a clock output to an FPGA pin (say AA24), which is available at a pin in an expansion connector of a board say J6(1). My question is, when i connect a target circuit to the board's J6(1) pin, should i take in account any impedance on the line that goes from the FPGA pin AA24 to the board pin J6(1)? Or can I assume that since the output is buffered there will be no voltage drop in the board output pin to the target circuit?

Best,

JM

Tags (5)
1 Solution

Accepted Solutions
Highlighted
Xilinx Employee
11,998 Views
Registered: ‎01-03-2008

> I'm trying to understand why the signal i probe at the FPGA clock output (with my 110 ohm

> pullup to 2.5V load connected to it) has a minimum voltage value of 480mA when drive=12

> instead of 0

Ok, the simple answer is that the output buffer doesn't have enough current capability to drive the output to 0.0V.

Ohms law says V=I*R and in your case you have 2.5V = I * 110ohm  or I = 2.5V/110ohm = 22.7mA.

The output buffer that you are using is specified as 12mA at Voh/Vol  (2.4V/0.8V) which is lower than 22.7mA so it can't get to 0.0V.

You measurements of 480mV indicate that the current at that voltage is 18.4mA ( (2.50-0.48)/110).  If I am reading the right number from the V-4 IBIS file this is within the indicated range.

[Pulldown]

Voltage  I(typ)       I(min)       I(max)

-------  ----------   -----------  ------------

0.4000   23.0500mA    16.8300mA    28.1400mA
0.5000   27.5200mA    20.1100mA    33.6200mA

You won't find any output buffer that will get to 0.0V, but the LVTTL_F_24 will get you closer.

Note - Edited to correct table from Pullup to Pulldown values

Message Edited by mcgett on 03-24-2010 11:37 AM
------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
32 Replies
Explorer
11,931 Views
Registered: ‎02-27-2010

Since you're "J6 pin 1" sounds like a standard 0.100" header, you're apparantly not looking at 100s of MHz in speed.  And since FPGAs are not good for analog drive, you must be looking for a digital signal.

PC board trace impedances typically only need to be considered for very high speed lines or signals with tight timing margins.  By adjusting the drive current of your I/O pin, you can get a better signal for most situations after you're already connected up and running but seeing slow settling on your signal.

The I/O pins don't have an impedance like analog line drivers.  What you see isn't the equivalent of an ideal driver with a series resistor but instead an active network which gives guaranteed logic transition voltages under specific current demands.  LVDS I/O are about the closest we come to the analog world in these parts but I still think it's a good distance from ideal.

Modern high speed board design includes IBIS simulations for those high speed or tight timing tolerance signals.  Most people working with development boards don't need this extreme level of detail expecially since your development board is already laid out and your only real option for change at this point is probably through drive level adjustment.

You also have the choice of multiple signalling standards which include source and end terminated topologies.

The only "voltage drop" typically associated with I/O pins is on a transitioning signal.

Highlighted
Explorer
11,919 Views
Registered: ‎05-15-2009

Thank you.

The signal i'm driving out from the FPGA is 6MHz, LVTTL. I'm considering such impedance because i'm driving a load with a termination of 110 ohm to 2.5V and when the clock reaches 0V, the voltage around the termination is not zero (rounds about 960mV). Hence, the only explanation i can get so far is that there must be an impedance (around 60 ohm) between the FPGA pin and the J6(1). Otherwise i would expect the voltage at the lçoad (probed right after the J6(1) pin) to be zero don't you think?

Yes,  the J6(1) is a 0.100 standard header. I use the ML402 Xilinx board.

Best,

JM

Highlighted
Explorer
11,915 Views
Registered: ‎02-27-2010

You've specified LVTTL.  Have you specified the current?  Is you LVTTL powered by a 3.3V VCCIO or 2.5V ?  I can't find the specific section in the device data sheet at the moment which specified the VCCIO needed for a specific I/O standard but if you're using a 2.5V supply you may want to change to LVCMOS_25.

Changing the drive current should get you to where you want to be.  If you get the IBIS file for your device, you should see the amount of current (min, max, typical) for the DC condition at the voltage in question.

Another problem you might be experiencing is improper grounding.  If you don't have an appropriate common ground between the two boards, you may have a diode drop through protection diodes.

- -

Ah, there it is: Page 253 of http://www.xilinx.com/support/documentation/user_guides/ug070.pdf shows the LVTTL requirements and other issues.

Message Edited by john.h on 03-24-2010 05:30 AM
Highlighted
Explorer
11,910 Views
Registered: ‎05-15-2009

Thank you John,

Yes, it's a 3.3V bank so LVTTL is fine. Changing the drive also changes the sink current of the FPGA clock source? I mean, the sink is equal to the drive current?

As for the grounds they are common, no prob here. The prob might be that the sink current may be less than the current driven by the load when the source clock signal is at low state..

Highlighted
Explorer
11,905 Views
Registered: ‎02-27-2010

The table on page 254 says the Voh and Vol values are specified at the drive strength currents.  The IBIS files will give you the precise curves as well.

Since your 110 ohm resistor is pulling 14mA at that high a voltage, you may be set for the 8mA drive current (or less).

The default DRIVE value should probably be 12mA (from a quick google that landed me on the DRIVE constraint) but the 960mV for the pulldown is more than 30mA for that DRIVE level so I'm guessing the drive was changed to 8mA.  The  12mA setting should provide a minimum of actually over 16mA according to the IBIS file with asteady voltage of 0.5V at most at that setting.  You can bump it up to 16mA if you wanted to guarantee 0.4V, again according to the IBIS file.

Are you certain you don't have two 100 ohm pullups to 2.5V on the one line?

Highlighted
Explorer
11,901 Views
Registered: ‎05-15-2009

Hi John,

My 110ohm resistor pulls 7.3mA at clock high (3.3) because it drops to 2.5V.

Yes, the default drive is 12mA (but how about the sink? is it the same?). To clear things up now i took a scope A of the clock signal, setting the drive to 12mA and the minimum observed voltage at the load terminals is 480mV. Without the load, the clock signal has -240mV average as low voltage (scope B).

Accoording to my calculations, when the signal B (without load) reaches 0V, we should observethe following with the load attached:

Isink = -2.5/110 = -22.7mA
Vload = 110*(-(0.0227 - 0.012) + 2.5 = 1.32V

And when the clock signal it reaches -240mV:

Isink = -(2.5+0.240)/110 = -24.9mA

Vload = 110*(-(0.0249 - 0.012) + 2.5 = 1.081V

which is not the 480mV. Do you see any mistake on my calculations?

I tried to download the IBIS for the Virtex 4 but it gives an error. I'm not sure about 100% the pullup but accoording to the load datasheet it seems that there is only one (i previously confused with pulldown)

Best,

JM

Message Edited by jmonteiro-dme on 03-24-2010 08:49 AM
Highlighted
Xilinx Employee
11,896 Views
Registered: ‎01-03-2008

jmonteiro-dme,

I read through this thread several times and there is a lot of confusing or unclear information in the various threads.

First, the LVCMOS IO drivers are balanced drivers and will have exhibit the same sink and source current characterisitics.  LVTTL will have a stronger sink than source current due to the IO standard requirements for Voh/Vol.

Second, the current that is sourced/sinked through the output buffer is not constant.  The current will be stronger at the beginning of the transition, meet or exceed the data sheet spec at the Voh/Vol points and will be much lower at the VCCO/GND levels.

Third, you are setup has unbalanced termination with VCCO at 3.3V and 110ohm termination to GND.  It isn't clear why you are doing this, but if you want balanced termination it should be set VCCO * 0.5 or 1.65V.

It isn't possible using the V-4 datasheet, pen and paper to determine what the Vmax and Vmin are with the termination scheme that you are using.  An IBIS simulation, with the specific IO standard, SLEW and DRIVE strength or the physically measuring this is the way to go.

It is very confusing when you reference a voltage measurement of a signal to another signal's, clock, voltage level especially when the other signal has a different termination style.   It would be more appropriate to discuss only the Vmax and Vmin (and over/undershoot if warranted) for the signal that you are concerned about.

Lastly, the clock signal that you are referring to with a -240mV Vmin is because the signal is unterminated and causing undershoot at your observation point.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
Highlighted
Explorer
11,894 Views
Registered: ‎02-27-2010

Your numbers arn't working.

"Without the load" you no longer have 110 ohms so your -240mV (which is a measurement error if your FPGA has no negative voltages) does not draw a load current through the disconnected 110 ohm resistor.

The I/O sink is a pull down to 0 volts so you won't manage to pull a finite resistor down to 0.0V unless you account for measurement errors such as the -240mV you saw.  If you plot a "load line" on the VI curve for the output drive versus current, you'll see what voltage you should end up with.  Since the IBIS module for DC drive current have a min, typ, and max value you should be able to determine your min, typ, and max operating points by superimposing your resistor load line on that graph.  Since 0V is 0mA for the sink current, your load line for the resistor would be drawn as a straight line with 0mA at 2.5V and 22.7mA at 0v. The intersection of theresistor line with the I/V curves from the I/O sink would give you youroperating points.

You said previously that you measured 960mV on the signal.  Now you're measuring 480mV?  The settled value for the 12mA drive through a 110 ohm pullup to 2.5V should give a worst-case value of between 400 and 500 mV.  Change the DRIVE to 16mA and your results will improve.

All loads will reduce the settled value of the voltage swings.  Whether source or sink, the DRIVE will provide current versus voltage curves that comply with the IBIS models.  Even if you don't ahve an IBIS simulator, the operating point your looking for is not too difficult to find within those text files.

For a digital system, you need to be concerned with Voh and Vol levels for your outputs and Vih and Vil levels for your inputs (the values are different to account for other issues such as reflections or noise).  You won't get 0.0V.  If that's your expectation, please rethink.

With the IBIS, load lines, and desired logic levels you should find everything you need.

Highlighted
Explorer
11,892 Views
Registered: ‎02-27-2010

mggett,

There's some information you're trying to get across in the above post which is a little inaccurate.  While drivers may be designed to be ideally balanced or ideally provide a stonger sink, the reality is buried in the IBIS files.  I've spent some time in IBIS files in the past and went into the Virtex-4 file to help support this fellow designer.

While finding the information to "talk numbers" about this particular situation [which I read as the signal is 3.3V LVTTL with a 110ohm termination to 2.5V and I'm assuming the signal is the clock recently referred to]  I had to go back through the "pull-up" and "pul-down" numbers a couple times and even google "IBIS pull-down" to verify I was looking at the right thing.  For the LVTTL_F_12 standard in the Virtex-4 - I checked back and forth a few times - the source current drive is actually more capable than the sink current drive at the ~900mV offset from rail important to the initial measurements.  Maybe I need to look again, but the numbers in the IBIS file weren't making sense for my expectations of stronger sink current.

Every family will be a little different but even the LVCMOS aren't the best balance in the one Spartan family we designed with recently.  The designers chose a less popular standard for the "best balance" available from that part according to the IBIS models.  The strengths of P channel and N channel transistors are different and the proper combination is selected to provide the varying currents.  While ideally the size and quantity of transistors is designed for a good match, the reality is what we get in the human-readable IBIS files.

I will happily admit if I'm wrong on this.  It's all about trying to help.

Highlighted
Explorer
9,661 Views
Registered: ‎05-15-2009

John, many thanks for your detail and professionalism.

You said:

"The settled value for the 12mA drive through a 110 ohm pullup to 2.5V should give a worst-case value of between 400 and 500 mV"

You saw this through the IBIS files? To understand how you got the "400 and 500 mV" interval is what I need. I wanted to download them but the link is not working. Also, i never worked with the IBIS..

Best,

JM

Highlighted
Explorer
9,659 Views
Registered: ‎02-27-2010

There was a time when I had never worked with IBIS files either.  While signal integrity tools were later made available in my workplace, I still could use the IBIS files to get I/V curves.

The link I used from the xilinx site is this one:

It brought up a funky java downloader in a window that first suggested a popup was blocked.  If you allow popups from Xilinx (I trust 'em) *or* have java running properly, the donloader from this link might work fine for you.  The file is just over 2MB in a zip format.

In the IBIS files you'll find a section for each standard.  The permutations on the standard are in comment headers at the front of the file so you should find the proper term to search on such as LVTTL_F_12 and jump right to the section.  There are 4 DC curves given for pullup (drive to positive rail) pulldown (drive to ground) as well as positive and ground clamps.  The voltages are given relative to the rail such that the 0.0V for the pullup is actually 3.3V on your board in the LVTTL case.

If you can get the file and start looking through the table formats, you'll see the raw information you could import into your favorite math program or spreadsheet to get a pretty min/typ/max I/V curve for your viewing pleasure.  While a full-fledged IBIS simulator would be great to have and readily use, napkin-style calculations are easily done from this raw data, at least at the DC level.

Highlighted
Explorer
9,657 Views
Registered: ‎05-15-2009

John,

I get an error downloading. After the java interface is set i get a message "Download integrity is invalid".

Can you e-mail me the files to freakforever at gmail dot com? Sorry i don't want to publicate my own personal e-mail, i use this for junk and others.

I'll get back to you as soon i understand how to extract the "400mVto 500mV" range like you did for minimum signal low at 12mA.

Best,

JM

Highlighted
Xilinx Employee
9,648 Views
Registered: ‎01-03-2008

John,

> There's some information you're trying to get across in the above post which is a little inaccurate.

> ....

> For the LVTTL_F_12 standard in the Virtex-4 - I checked back and forth a few times - the

> source current drive is actually more capable than the sink current drive at the ~900mV

> offset from rail important to the initial measurements.

You are right, I made a couple mistakes in my post and let's see if I can correct them here.

A simplified and nominal table for LVTTL and LVCMOS 3.3V

LVTTL   LVCMOS

VCCO        3.3V    3.3V

Voh 12mA @  2.4V    2.9V

Vil 12mA @  0.8V    0.8V

GND         0.0V    0.0V

In both cases the Voh and Vil are not 100% balanced relative to the VCCO and GND settings.

The LVTTL standard will have a more balanced current profile between source and sink as the 12mA current is specified at VCC-0.7V and GND+0.8V, while LVCMOS standard is at VCC-0.4 and GND+0.8V.  In both cases the source current will be stronger than the sink (which I had reversed in my previous post).

There are other nuances at play here as the LVTTL standard could have a VCCO supply of 3.15V (-5%) while still having to maintain 12mA at Voh=2.4V (which will make the source stronger at 3.3V).  In contrast the LVCMOS standard Voh is measured a VCCO-0.4V and moves Voh to 2.75V with the corresponding drop in VCCO to 3.15V (-5%).

All of this is wrapped up into the IBIS models along with the real sizing and process variations for the NMOS and PMOS transitors that make up the output buffer, but for simple sanity checks can be ignored.   For real signal integrity work, using anything other than the IBIS models or the encrypted HSPICE models for the IOs would not be an acceptable design practice.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
Highlighted
Explorer
9,647 Views
Registered: ‎05-15-2009

Hi John,

Thank you so much for the files. Accordingly to your valuable orientations i got to the pullup values and I see

2.5000      -65.0800mA          -47.6700mA          -78.9100mA

I don't understand the following, can you help me clarify?

1) what you mean with "The voltages are given relative to the rail such that the 0.0V for the pullup is actually 3.3V on your board in the LVTTL case."

2) The pullup voltage is an external pullup like in my case or is it internal?

3) Also I'm missing how can I cross my110ohm termination with these values to get the range..

It should be simple but i never worked with IBIS.

Best,

JM

Highlighted
Xilinx Employee
9,642 Views
Registered: ‎01-03-2008

JM,

What are you really trying to do in this application?

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
Highlighted
Explorer
9,639 Views
Registered: ‎05-15-2009

I'm trying to understand why the signal i probe at the FPGA clock output (with my 110 ohm pullup to 2.5V load connected to it) has a minimum voltage value of 480mA when drive=12 instead of 0. I'm trying to figure it out from the IBIS John kindly provided to me however i don't understand to where the pullup voltage in the IBIS is measured.

Best,

JM

Highlighted
Explorer
9,638 Views
Registered: ‎02-27-2010

The "pullup" is the ability of the pull-up drive transistor in the FPGA to source current.  Since no current means no voltage drop, the 0.0V delta means 0V from the positive rail.  If you have an output driving a 3.3V signal and the voltage difference of 0.0V is seen on the output (you're actually getting 3.3V) you'll have no current.  Drag this 2.2V signal WAY way down and the FPGA fights to try to bring the output back up to 3.3V but down at 0.8 volts, that super heavy load is sourcing current somewhere between 47.67mA and 78.91mA, typically around 65.08mA.  The 2.5V delta is the difference between the 3.3V rail and the actual voltage.

[But since you're interested in the  low voltage, the pulldown is the set of curves you want.  To get 480mV output, your current will be representative of the table entries around 0.400 and 0.500 volts.]

The voltages are the static DC voltages viewed at the I/O pin based on the amount of current sourced or sunk (sinked?) through the I/O pin due to whatever external loads there may be.

To get your operating point, draw a graph like I explained previously showing your IBIS derived current versus voltage waveforms and superimpose the resistor "line" from its zero current termination voltage to its 0 voltage fully-engaged current.  Every point along that line is a possible resistor voltage/current operating point.  It's only when this line is between the max and min current values that your resistor and driver will be in static equalibrium.

The dynamic nature of the drivers isn't as easily derived manually from these files but for static analysis, they do a good job.

Message Edited by john.h on 03-24-2010 11:09 AM
Highlighted
Xilinx Employee
11,999 Views
Registered: ‎01-03-2008

> I'm trying to understand why the signal i probe at the FPGA clock output (with my 110 ohm

> pullup to 2.5V load connected to it) has a minimum voltage value of 480mA when drive=12

> instead of 0

Ok, the simple answer is that the output buffer doesn't have enough current capability to drive the output to 0.0V.

Ohms law says V=I*R and in your case you have 2.5V = I * 110ohm  or I = 2.5V/110ohm = 22.7mA.

The output buffer that you are using is specified as 12mA at Voh/Vol  (2.4V/0.8V) which is lower than 22.7mA so it can't get to 0.0V.

You measurements of 480mV indicate that the current at that voltage is 18.4mA ( (2.50-0.48)/110).  If I am reading the right number from the V-4 IBIS file this is within the indicated range.

[Pulldown]

Voltage  I(typ)       I(min)       I(max)

-------  ----------   -----------  ------------

0.4000   23.0500mA    16.8300mA    28.1400mA
0.5000   27.5200mA    20.1100mA    33.6200mA

You won't find any output buffer that will get to 0.0V, but the LVTTL_F_24 will get you closer.

Note - Edited to correct table from Pullup to Pulldown values

Message Edited by mcgett on 03-24-2010 11:37 AM
------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
Highlighted
Explorer
9,623 Views
Registered: ‎05-15-2009

Thank you mcget, i got it clearly.

Just one last question: is it correct for me to think that at 0V the current in the circuit will be 12 - 22.7 = 10.7mA? An that this is because the clock buffer is not able to sink to GND that ammount of current?

Best,

JM

Highlighted
Explorer
9,094 Views
Registered: ‎02-27-2010

As already mentioned, you can't pull the signal to a static ground if you have any static current.  If you have no static current, you can see ground.  No logic requires a ground level for ground reference I/O.

If you use a termination resistor, you will always be some voltage away from ground for the pulldown or from VCCIO for the positive rail.

Highlighted
Explorer
9,088 Views
Registered: ‎05-15-2009

John,

I remembered that the 24mA source can pull the output voltage to almost zero with the -22.A current. But is this simply because the pulldown resistor is lower?

Best,

JM

Highlighted
Explorer
9,084 Views
Registered: ‎02-27-2010

It's because there are more and larger transistors used to pull the signal down.

But if you blindly start trying to drive your signal harder, you'll start seeing a severe degradation in your signal fidelity.  Driving too hard often leads to severe overshoot and resulting ringing from the reflections.  If you're generating a clock and trying to open up that "eye" you may be much better served by using an A/C termination (110 ohms to a cap rather than 3.3V) which is effective for clocks where the DC balance is static.  For more random signals, a termination voltage between the two extremes could be better.

You might also have better results still by using a source series termination to a single destination.   Bymatching the source termination to the line impedance, your voltage initially only goes halfway but doubles in voltage upon hitting the reflection of an unterminated receiver and recovers to 100% voltage.

Perhaps you should take a step back and answer mcgett's question:

"What are you really trying to di in this application?"

Terminations are often used only where they're needed.  Clocks are one superb example where good terminations are necessary.  But your receiver probably has a well established Vih and Vil set of voltages it needs that are far from 0.0V and 2.5V.  Are you running a very long line through a twisted-pair cable or are you entirely on PCboards with a length of less than 11 inches?  What is the clock frequency you're using and do you need as little jitter as possible or are you just trying to avoid double clocking?

These are all pieces of information that an IBIS simulator would work with either as input or output.  Engineering is about determining what you need and what you want and landing a design somewhere within those limits.  What do you need and what do you want?

Highlighted
Explorer
9,082 Views
Registered: ‎05-15-2009

Hi john.

As i said, i simply wanted to understand what i was observing/probing. I already have a clock source, which is the ML402 and the clock target, which is a digital I/O board which in turn has an internal termination to 2.5V.

With this being said, i don't need to perform any termination. I just wanted to understand why the signal i was probing between the source and the target didn't drop to zero. Now i do understand thanks to you guys.

What i still haven't clearly understand is the transistor pulldown. Earlier you said the pull down of the source was a resistor. Can't i see it as a resistor?

Best,

JM

Highlighted
Explorer
9,078 Views
Registered: ‎02-27-2010

Please tell me which response (timestamp, for instance) where I said a pulldown resistor was involved?  I'll try to elaborate on what I said or misstated.

I did explicitly state the driver is not like other devices which may look more like an ideal driver with a series resistor.  And I spoke of transistors on occasion.

The output drivers are transistors (no resistors for these intents and purposes) which vary in size and/or number to deliver the various drive strenghts, either source or sink.

Highlighted
Explorer
9,075 Views
Registered: ‎05-15-2009

You are correct, i misinterpreted the following:

"The I/O sink is a pull down to 0 volts so you won't manage to pull a finite resistor down to 0.0V unless you account for measurement errors such as the -240mV you saw."

Do you have any reference documents i can read so i can understand further how the current is driven/sink out from the buffer?

Let me thank you once again for your great valuable input.

Best,

JM

Highlighted
Explorer
9,072 Views
Registered: ‎02-27-2010

I don't believe I can point you to a succinct source for information.

My knowledge comes from a deep history starting with Semiconductor Physics in college, databooks like from TI in the '80s where illustrations of the electronics were presented to the transistor level, and occasional information  in FPGA vendor data sheets or applications notes talking about the I/O drivers.  Reading about the occasional technology bits like the 6T SRAM cell aslo gives insight into how transistors interface with each other to give us the bulding block we need to do higher level design.  Delving into voltage specifications across families of devices and logic interface types often presents good discussions on noise margins and other issues.  Items pertinent to signal fidelity like reflections in transmission line theory start in courses and find their way into app notes to refresh my understanding.

If you want advanced understanding, a Howard Johnson text on "Black Magic" would give you some tremendous stuff.  But as far as the basics?  I'm not sure where to point you.

Highlighted
Explorer
9,068 Views
Registered: ‎05-15-2009

Hi John,

Thank you. I was particulary interested in the sink circuitry. I can understand an impedance termination but not a transistor one. Anyway, the high-level concept is the same right? If a termination exists, there must exist a voltage drop around the termination.

Best,

JM

Highlighted
Explorer
9,065 Views
Registered: ‎02-27-2010

To me your statement sounds like "I can understand a spring but I can't understand a muscle."  The output of the circuit is the muscle, pulling the spring [the resistor] up or pulling it down.  It can only pull so hard depending on how far away the spring is.  More or larger transistors equal more muscle.  It may be easier to pull something up or down depending on the muscles involved.

The transistors in these cases are not terminations. They may have a dynamic impedance at a certain voltage (a small change in voltage results in a small change of current) but they're intended do drive as hard as they can.  The source terminations I spoke of are like the "ideal muscles" pulling with a spring rather than an ideal transistor driving in series with a resistor.  The initial deflection is halfway until the other end of the driven spring realizes it's unconnected and lets go.

So please don't think of transistors as terminations.  They're at the source, not the terminus.  Transistors cannot pull a real load to the rail they're pulling toward.  Bigger muscle just means you get closer.

Please take the analogy for what it's intended - a rough physical equivalent - and don't read too much into the specifics of the analogy.

Message Edited by john.h on 03-24-2010 06:20 PM
Highlighted
Explorer
9,056 Views
Registered: ‎05-15-2009

Hhm, so for an lvttl say we have the following push-pull driver

and when the input is 0V, current will flow down from the input through the pull-down resistor and since there will be a voltage drop around this resistor, we will not see the 0V at the output but something above that am i right?

reverting to your analogy, in this case the muscle will be pulling down the spring because of the inverse current and since it has a "strength", it will be visible at the output. Is this correct?

Best,

JM