02-22-2011 02:06 PM
My goal is to put some user data (specifically, inputs for an FFT core) in the JS28F256P30 flash device on the ML605 board, then read it out using a simple VHDL interface. I've successfully programmed the flash through Impact and used readback to verify that the contents match my input file. Judging by the JS28F256P30 data sheet, the device starts up in asynchronous read mode by default, and reading from it should be fairly straightforward; however, when I attempt this, I just see ones on the data bus. Here is my VHDL code:
FPGA_FWE_B <= '1';
FLASH_WAIT <= '0';
FPGA_FOE_B <= '0';
FPGA_FCS_B <= '0';
P30_CS_SEL <= '0';
fl_addr_int <= "000000000000000000000011";
LEDs8 <= FLASH_D(7 downto 0);
FLASH_A <= fl_addr_int;
I am just looking at one address for now, in an attempt to verify the read operation. Does anyone know what's wrong, or have an example of something similar? I've been looking around, but it seems as though people usually just use the flash for storing configuration files and software, and don't try to put raw data in it and then read from specific addresses like this.
02-24-2011 08:55 AM
02-24-2011 09:35 AM - edited 02-24-2011 09:36 AM
As many as you like. That code that you see is not happening inside any process; since I am only trying to look at the one address for now, I am just putting the address on the lines and letting it sit there forever. The data bus is perpetually connected to the LEDs as well. I did this in a deliberate attempt to rule out timing issues.
The only downside to this that I can think of, is that the flash might need to see some sort of rising or falling edge before it puts data on the bus -- but that shouldn't be the case in asynchronous read mode, should it? Or am I missing something?
02-28-2011 08:14 AM
That should work, assuming that you have the various control signals as they should be - from timing diagram in data sheet,
ADV#, CE#, OE# all 0, RST# at 1.
02-28-2011 11:52 AM - edited 02-28-2011 11:53 AM
I don't have access to the #ADV and #RST signals from the FPGA, but from the ML605 board's schematics, it seems that the #ADV pin on the flash chip is tied low, and the #RST chip is tied high. So I'm mystified as to why it doesn't work. From studying the schematic, I think I need to change P30_CS_SEL to '1' to get the CE pin on the flash chip to go low; but even that doesn't help.
07-29-2011 01:53 PM
I was wondering if you got this to work? I have an Avnet virtex-5 board which uses a 128P30 flash device and am seeing the same behavior. I am pulling ADV#, CE#, and OE# low, and WE# and CLK high. I'm setting the address to one which I've verified has data through a readback in IMPACT. All I get back is logic high on all data lines.
05-08-2012 05:55 AM
cgauer, I was wondering if you managed this to work. I was planning on using the BPI memory on the ML605 to store some data for DAC output.
Could you manage to work around this problem?