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Anonymous
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10.1 isim on Linux not seeing latest changes to vhdl files

I'm running ise 10.1 on a Linux system, coding in vhdl, and this latest project is

for an XC9572XL.  (I use 10.1 because we are still supporting some older Spartan

and 9500 parts.)  On this project, I accidentally selected the implementation file

(xxx.vhd) rather than the testbench (xxx_tb.vhd) and clicked on behavioral simulation.

I got a bunch of red lines, realized I'd started the sim on the wrong file, but from

then on, all I get is a sim of the old files.  Even closing ise are restarting it keeps

simulating the old files.  I created a new project and copied in the vhd and ucf files,

that worked ONE TIME, then back to the same old stuff.  I then deleted the entire

isim directory tree and it sims the latest version of the files.  I'm not absolutely

sure simulating the wrong file caused this, but that's when this problem started.  Is there a

setting somewhere that will make it use the latest vhd files, especially if they

have been modified?  Deleting the isim tree seems awfully brutal.  Shouldn't it

use time stamps to keep track of obsolete files?  (My clock is set properly, and

file times are correct.)

 

Thanks for any suggestions anyone can offer,

 

Jon

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Xilinx Employee
Xilinx Employee
2,597 Views
Registered: ‎07-16-2008

Re: 10.1 isim on Linux not seeing latest changes to vhdl files

The tool is expected to catch the change in simulation sources.

What if you run "Cleanup Project Files" from Project menu?

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