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david.hoffman
Explorer
Explorer
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Registered: ‎07-18-2011

10G MAC Example Design

Hello,

 

I'm trying to simulate the example design that comes with the 10-Gigabit Ethernet MAC v14.0 core. It's failing during elaboration:

 

Vivado Simulator 2014.4
Copyright 1986-1999, 2001-2014 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2014.4/bin/unwrapped/win64.o/xelab.exe -wto b0ae628e58d044be9919b886b55c6786 --debug typical --relax -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot ten_gig_eth_mac_64b_demo_tb_behav xil_defaultlib.ten_gig_eth_mac_64b_demo_tb xil_defaultlib.glbl -log elaborate.log
Multi-threading is on. Using 2 slave threads.
Starting static elaboration
ERROR: [VRFC 10-426] cannot find port O1 on this module [C:/Users/dhoffman/Projects/fpga/src/main/ipcores/ten_gig_eth_mac_64b/ten_gig_eth_mac_64b_example/ten_gig_eth_mac_64b_example.srcs/sources_1/ip/ten_gig_eth_mac_64b/ten_gig_eth_mac_64b_funcsim.v:64439]
ERROR: [VRFC 10-426] cannot find port O2 on this module [C:/Users/dhoffman/Projects/fpga/src/main/ipcores/ten_gig_eth_mac_64b/ten_gig_eth_mac_64b_example/ten_gig_eth_mac_64b_example.srcs/sources_1/ip/ten_gig_eth_mac_64b/ten_gig_eth_mac_64b_funcsim.v:64440]
ERROR: [VRFC 10-426] cannot find port O3 on this module [C:/Users/dhoffman/Projects/fpga/src/main/ipcores/ten_gig_eth_mac_64b/ten_gig_eth_mac_64b_example/ten_gig_eth_mac_64b_example.srcs/sources_1/ip/ten_gig_eth_mac_64b/ten_gig_eth_mac_64b_funcsim.v:64441]
ERROR: [VRFC 10-426] cannot find port frame_start on this module [C:/Users/dhoffman/Projects/fpga/src/main/ipcores/ten_gig_eth_mac_64b/ten_gig_eth_mac_64b_example/ten_gig_eth_mac_64b_example.srcs/sources_1/ip/ten_gig_eth_mac_64b/ten_gig_eth_mac_64b_funcsim.v:64442]
ERROR: [VRFC 10-426] cannot find port p_1_in on this module [C:/Users/dhoffman/Projects/fpga/src/main/ipcores/ten_gig_eth_mac_64b/ten_gig_eth_mac_64b_example/ten_gig_eth_mac_64b_example.srcs/sources_1/ip/ten_gig_eth_mac_64b/ten_gig_eth_mac_64b_funcsim.v:64443]
ERROR: [VRFC 10-426] cannot find port reset on this module [C:/Users/dhoffman/Projects/fpga/src/main/ipcores/ten_gig_eth_mac_64b/ten_gig_eth_mac_64b_example/ten_gig_eth_mac_64b_example.srcs/sources_1/ip/ten_gig_eth_mac_64b/ten_gig_eth_mac_64b_funcsim.v:64444]
ERROR: [VRFC 10-426] cannot find port rx_axis_aresetn on this module [C:/Users/dhoffman/Projects/fpga/src/main/ipcores/ten_gig_eth_mac_64b/ten_gig_eth_mac_64b_example/ten_gig_eth_mac_64b_example.srcs/sources_1/ip/ten_gig_eth_mac_64b/ten_gig_eth_mac_64b_funcsim.v:64445]
ERROR: [VRFC 10-426] cannot find port rx_clk0 on this module [C:/Users/dhoffman/Projects/fpga/src/main/ipcores/ten_gig_eth_mac_64b/ten_gig_eth_mac_64b_example/ten_gig_eth_mac_64b_example.srcs/sources_1/ip/ten_gig_eth_mac_64b/ten_gig_eth_mac_64b_funcsim.v:64446]
ERROR: [VRFC 10-426] cannot find port rx_configuration_vector on this module [C:/Users/dhoffman/Projects/fpga/src/main/ipcores/ten_gig_eth_mac_64b/ten_gig_eth_mac_64b_example/ten_gig_eth_mac_64b_example.srcs/sources_1/ip/ten_gig_eth_mac_64b/ten_gig_eth_mac_64b_funcsim.v:64447]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.

 

If it matters, I'm using an evaluation license for both Vivado and the 10G MAC downloaded an evaluation license of the core. 

 

Thank you,

David

 

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