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Visitor
Visitor
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Registered: ‎02-22-2015

2014.3 VIVADO Simulator error [USF-XSim-62]

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Hi,

 

I am trying to simulate my project, but I keep receiving an error:

 

ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console ouput or ' ' file for more information.

 

I tried looking at other threads and tried changing output reg A, but it didn't make a difference. Thanks in advance!

 

`timescale 1ns / 1ps

module SYS(c, Data, clk, B, Cout, A);
   // paramter n=4;
   input [4:0] c;
   input [3:0] Data;
   input clk;
   input [3:0] B;
   output Cout;
   output reg [3:0] A;
    reg [3:0] bus  ;
    wire [3:0]PAout;
    wire [3:0] gate;
    initial A=0;
    
    
    //register A
    always @(posedge clk)
    begin
    if (c[0])
        A <= 4'b0000;
    else if (c[1])
        A <= A + 1;
    else if (c[2])
        A <= bus;
    end
    
    //mux
    always @(c[3] or Data or PAout)
    begin
    if (c[3]) 
        bus = Data;
    else
        bus = PAout;
    end
    
    always @(posedge clk)
    begin
    assign gate = B ^ c[4];
    end
    
    //PA
    always @( A or gate or c[4])
    begin
    if (c[4])
        A = A - gate;
    else
        A = A + gate;
    end
    
endmodule

 TESTBENCH:

`timescale 1ns / 1ps

module SIMSYS1();
   reg clk;
   reg [4:0] c;
   reg [3:0] Data, B;
   wire [3:0] A;
   
SYS x(c, Data, clk, B, Cout, A);
   
   initial
   begin
    clk = 0, Data = 0, B = 0, c = 0;
    forever #5 clk = ~clk;
        #4  c[0] = 1; c[1] = 0; c[2] = 0; // reset
        #10  c[0] = 0; c[1] = 0; c[2] = 1; C[3] = 0; Data = 6; //Load
        #10 c[0] = 0; c[1] = 1; c[2] = 0; // increment
        #10  c[0] = 0; c[1] = 0; c[2] = 1; c[3] = 1; c[4] = 0; B = 6; end  // Adding A + 6
        #10 begin c[0] = 0; c[1] = 0; c[2] = 1; c[3] = 1; c[4] = 1; B = 5; end  // Subtracting A - 5
        #10 $finish;
   end
endmodule

 

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Xilinx Employee
Xilinx Employee
32,385 Views
Registered: ‎02-16-2014

Re: 2014.3 VIVADO Simulator error [USF-XSim-62]

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Hi,

 

It seems there are some syntax errors in your test bench.With this tets bench and module I am able to run the simulation.

 

`timescale 1ns / 1ps
module SIMSYS1();
reg clk;
reg [4:0] c;
reg [3:0] Data, B;
wire [3:0] A;

SYS x(c, Data, clk, B, Cout, A);

initial
begin
clk = 0;Data = 0;B = 0;c = 0;
forever #5 clk = ~clk;
#4 c[0] = 1; c[1] = 0; c[2] = 0; // reset
#10 c[0] = 0; c[1] = 0; c[2] = 1;c[3] = 0; Data = 6; //Load
#10 c[0] = 0; c[1] = 1; c[2] = 0; // increment
#10 c[0] = 0; c[1] = 0; c[2] = 1; c[3] = 1; c[4] = 0; B = 6; // Adding A + 6
#10 begin c[0] = 0; c[1] = 0; c[2] = 1; c[3] = 1; c[4] = 1; B = 5; end // Subtracting A - 5
#10 $finish;
end
endmodule

 Top module:

 

`timescale 1ns / 1ps

module SYS(c, Data, clk, B, Cout, A);
   // paramter n=4;
   input [4:0] c;
   input [3:0] Data;
   input clk;
   input [3:0] B;
   output Cout;
   output reg [3:0] A;
    reg [3:0] bus  ;
    wire [3:0]PAout;
    reg [3:0] gate;
    initial A=0;
    
    
    //register A
    always @(posedge clk)
    begin
    if (c[0])
        A <= 4'b0000;
    else if (c[1])
        A <= A + 1;
    else if (c[2])
        A <= bus;
    end
    
    //mux
    always @(c[3] or Data or PAout)
    begin
    if (c[3]) 
        bus = Data;
    else
        bus = PAout;
    end
    
    always @(posedge clk)
    begin
    assign gate = B ^ c[4];
    end
    
    //PA
    always @( A or gate or c[4])
    begin
    if (c[4])
        A = A - gate;
    else
        A = A + gate;
    end
    
endmodule

 

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Visitor
Visitor
20,482 Views
Registered: ‎02-22-2015

Re: 2014.3 VIVADO Simulator error [USF-XSim-62]

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It is actually Vivado 2014.4
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Xilinx Employee
Xilinx Employee
20,477 Views
Registered: ‎02-16-2014

Re: 2014.3 VIVADO Simulator error [USF-XSim-62]

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Hi,

 

If you want to use gate inside the always block it should be declared as reg.

 

Declare gate as reg then it should work.

 

 always @(posedge clk)
    begin
     assign gate = B ^ c[4];
    end
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Xilinx Employee
Xilinx Employee
20,476 Views
Registered: ‎02-16-2014

Re: 2014.3 VIVADO Simulator error [USF-XSim-62]

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And also, 

 

I would suggest you to refer verilog LRM or any text book to check the usage of those constructs.

Many resources are availble on web and you can refer to the attached LRM also.

 

 

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Visitor
Visitor
20,461 Views
Registered: ‎02-22-2015

Re: 2014.3 VIVADO Simulator error [USF-XSim-62]

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Hi, I followed your suggestion, but unfortunately I am receiving the same error.

 

`timescale 1ns / 1ps

module SYS(c, Data, clk, B, Cout, A);
   // paramter n=4;
   input [4:0] c;
   input [3:0] Data;
   input clk;
   input [3:0] B;
   output Cout;
   output reg [3:0] A;
    reg [3:0] bus  ;
    wire [3:0]PAout;
    reg [3:0] gate;
    initial A=0;
    
    
    //register A
    always @(posedge clk)
    begin
    if (c[0])
        A <= 4'b0000;
    else if (c[1])
        A <= A + 1;
    else if (c[2])
        A <= bus;
    end
    
    //mux
    always @(c[3] or Data or PAout)
    begin
    if (c[3]) 
        bus = Data;
    else
        bus = PAout;
    end
    
    always @(posedge clk)
    begin
    gate = B ^ c[4];
    end
    
    //PA
    always @( A or gate or c[4])
    begin
    if (c[4])
        A = A - gate;
    else
        A = A + gate;
    end
    
endmodule

 

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Xilinx Employee
Xilinx Employee
20,448 Views
Registered: ‎10-24-2013

Re: 2014.3 VIVADO Simulator error [USF-XSim-62]

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Hi,
Refer to the tcl console and see what is the exact error that you are seeing. The message that you posted just says that there is an error.
ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console ouput or ' ' file for more information.
Thanks,Vijay
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
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Xilinx Employee
Xilinx Employee
32,386 Views
Registered: ‎02-16-2014

Re: 2014.3 VIVADO Simulator error [USF-XSim-62]

Jump to solution

Hi,

 

It seems there are some syntax errors in your test bench.With this tets bench and module I am able to run the simulation.

 

`timescale 1ns / 1ps
module SIMSYS1();
reg clk;
reg [4:0] c;
reg [3:0] Data, B;
wire [3:0] A;

SYS x(c, Data, clk, B, Cout, A);

initial
begin
clk = 0;Data = 0;B = 0;c = 0;
forever #5 clk = ~clk;
#4 c[0] = 1; c[1] = 0; c[2] = 0; // reset
#10 c[0] = 0; c[1] = 0; c[2] = 1;c[3] = 0; Data = 6; //Load
#10 c[0] = 0; c[1] = 1; c[2] = 0; // increment
#10 c[0] = 0; c[1] = 0; c[2] = 1; c[3] = 1; c[4] = 0; B = 6; // Adding A + 6
#10 begin c[0] = 0; c[1] = 0; c[2] = 1; c[3] = 1; c[4] = 1; B = 5; end // Subtracting A - 5
#10 $finish;
end
endmodule

 Top module:

 

`timescale 1ns / 1ps

module SYS(c, Data, clk, B, Cout, A);
   // paramter n=4;
   input [4:0] c;
   input [3:0] Data;
   input clk;
   input [3:0] B;
   output Cout;
   output reg [3:0] A;
    reg [3:0] bus  ;
    wire [3:0]PAout;
    reg [3:0] gate;
    initial A=0;
    
    
    //register A
    always @(posedge clk)
    begin
    if (c[0])
        A <= 4'b0000;
    else if (c[1])
        A <= A + 1;
    else if (c[2])
        A <= bus;
    end
    
    //mux
    always @(c[3] or Data or PAout)
    begin
    if (c[3]) 
        bus = Data;
    else
        bus = PAout;
    end
    
    always @(posedge clk)
    begin
    assign gate = B ^ c[4];
    end
    
    //PA
    always @( A or gate or c[4])
    begin
    if (c[4])
        A = A - gate;
    else
        A = A + gate;
    end
    
endmodule

 

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Visitor
Visitor
20,437 Views
Registered: ‎02-22-2015

Re: 2014.3 VIVADO Simulator error [USF-XSim-62]

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I noticed that you changed the commas in the test bench to semi-colons and I had also forgotten to omit "end" from one of the lines.. I copy and pasted the code you gave me and ran the simulation, but I am still receiving the same error.

 

ERROR: [Simtcl 6-50] Simulation engine failed to start: A valid license was not found for simulation. Please run the Vivado License Manager for assistance in determining which features and devices are licensed for your system.
Please see the Tcl Console or the Messages for details.

ERROR: [USF-XSim-62] 'simulate' step failed with errors. Please check the Tcl console or log files for more information.

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Visitor
Visitor
20,431 Views
Registered: ‎02-22-2015

Re: 2014.3 VIVADO Simulator error [USF-XSim-62]

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OK, it works now after I fixed the license issue. Thank you!
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Newbie
Newbie
13,167 Views
Registered: ‎04-05-2016

Re: 2014.3 VIVADO Simulator error [USF-XSim-62]

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Could you tell me how to fix the license issue ? Thank you !!

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Registered: ‎04-18-2016

Re: 2014.3 VIVADO Simulator error [USF-XSim-62]

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while the following is my code ,one of my partner had help me try the simulation behaviour on his computer and it succeed! what's wrong on my computer . anyone can tell me ?

error:

  • [USF-XSim 62] 'compile' step failed with error(s) while executing 'D:/vivadoWS/project_1/project_1.sim/sim_1/behav/compile.bat' script. Please check that the file has the correct 'read/write/execute' permissions and the Tcl console output for any other possible errors or warnings.

 

module projecttow(out, a, b, sl);


@pulim wrote:

Hi,

 

It seems there are some syntax errors in your test bench.With this tets bench and module I am able to run the simulation.

 

`timescale 1ns / 1ps
module SIMSYS1();
reg clk;
reg [4:0] c;
reg [3:0] Data, B;
wire [3:0] A;

SYS x(c, Data, clk, B, Cout, A);

initial
begin
clk = 0;Data = 0;B = 0;c = 0;
forever #5 clk = ~clk;
#4 c[0] = 1; c[1] = 0; c[2] = 0; // reset
#10 c[0] = 0; c[1] = 0; c[2] = 1;c[3] = 0; Data = 6; //Load
#10 c[0] = 0; c[1] = 1; c[2] = 0; // increment
#10 c[0] = 0; c[1] = 0; c[2] = 1; c[3] = 1; c[4] = 0; B = 6; // Adding A + 6
#10 begin c[0] = 0; c[1] = 0; c[2] = 1; c[3] = 1; c[4] = 1; B = 5; end // Subtracting A - 5
#10 $finish;
end
endmodule

 Top module:

 

`timescale 1ns / 1ps

module SYS(c, Data, clk, B, Cout, A);
   // paramter n=4;
   input [4:0] c;
   input [3:0] Data;
   input clk;
   input [3:0] B;
   output Cout;
   output reg [3:0] A;
    reg [3:0] bus  ;
    wire [3:0]PAout;
    reg [3:0] gate;
    initial A=0;
    
    
    //register A
    always @(posedge clk)
    begin
    if (c[0])
        A <= 4'b0000;
    else if (c[1])
        A <= A + 1;
    else if (c[2])
        A <= bus;
    end
    
    //mux
    always @(c[3] or Data or PAout)
    begin
    if (c[3]) 
        bus = Data;
    else
        bus = PAout;
    end
    
    always @(posedge clk)
    begin
    assign gate = B ^ c[4];
    end
    
    //PA
    always @( A or gate or c[4])
    begin
    if (c[4])
        A = A - gate;
    else
        A = A + gate;
    end
    
endmodule

 



@pulim wrote:

Hi,

 

It seems there are some syntax errors in your test bench.With this tets bench and module I am able to run the simulation.

 

`timescale 1ns / 1ps
module SIMSYS1();
reg clk;
reg [4:0] c;
reg [3:0] Data, B;
wire [3:0] A;

SYS x(c, Data, clk, B, Cout, A);

initial
begin
clk = 0;Data = 0;B = 0;c = 0;
forever #5 clk = ~clk;
#4 c[0] = 1; c[1] = 0; c[2] = 0; // reset
#10 c[0] = 0; c[1] = 0; c[2] = 1;c[3] = 0; Data = 6; //Load
#10 c[0] = 0; c[1] = 1; c[2] = 0; // increment
#10 c[0] = 0; c[1] = 0; c[2] = 1; c[3] = 1; c[4] = 0; B = 6; // Adding A + 6
#10 begin c[0] = 0; c[1] = 0; c[2] = 1; c[3] = 1; c[4] = 1; B = 5; end // Subtracting A - 5
#10 $finish;
end
endmodule

 Top module:

 

`timescale 1ns / 1ps

module SYS(c, Data, clk, B, Cout, A);
   // paramter n=4;
   input [4:0] c;
   input [3:0] Data;
   input clk;
   input [3:0] B;
   output Cout;
   output reg [3:0] A;
    reg [3:0] bus  ;
    wire [3:0]PAout;
    reg [3:0] gate;
    initial A=0;
    
    
    //register A
    always @(posedge clk)
    begin
    if (c[0])
        A <= 4'b0000;
    else if (c[1])
        A <= A + 1;
    else if (c[2])
        A <= bus;
    end
    
    //mux
    always @(c[3] or Data or PAout)
    begin
    if (c[3]) 
        bus = Data;
    else
        bus = PAout;
    end
    
    always @(posedge clk)
    begin
    assign gate = B ^ c[4];
    end
    
    //PA
    always @( A or gate or c[4])
    begin
    if (c[4])
        A = A - gate;
    else
        A = A + gate;
    end
    
endmodule

 





input a, b, sl;
output out;
wire nsl, sela, selb;
assign nsl = ~sl;
assign sela = a & nsl;
assign selb = b & sl;
assign out = sela | selb;
endmodule

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