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Observer
Observer
10,320 Views
Registered: ‎09-13-2015

2014.3 VIVADO Webpack Simulator

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I'm trying to simulate a very simple VHDL code but for some reasons I can't get it to work. I looked at my source code and didn't find any errors and the simulation doesn't yield any errors and warnings. All the values for my input are U for some reasons.

Can anybody help?

 

Here's my code:

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity dff_hw is
    port (clk, rst, d: in  std_logic;
          q: out std_logic);
end entity;
architecture behavioral of dff_hw is
begin
   process (clk, rst)
   begin
     if (rst ='1') then
        q <='0';
     elsif (clk'event and clk ='1') then
           q <= d;
     end if;
   end process;
end architecture;

Waveform.png
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Observer
Observer
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Registered: ‎09-13-2015

Re: 2014.3 VIVADO Webpack Simulator

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Hi @rajeshtu

Works swimmingly! Thanks a lot for your help.

View solution in original post

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Observer
Observer
10,317 Views
Registered: ‎09-13-2015

Re: 2014.3 VIVADO Webpack Simulator

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Here's a better picture of what the waveform looks.

Thanks!

waveform_2.png
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Xilinx Employee
Xilinx Employee
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Registered: ‎04-16-2012

Re: 2014.3 VIVADO Webpack Simulator

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Hi @serge1973

 

Did you have testbench? If yes, share it here.

 

If no, how are you toggling the clock?

 

Thanks,

Vinay

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Xilinx Employee
Xilinx Employee
10,289 Views
Registered: ‎08-01-2008

Re: 2014.3 VIVADO Webpack Simulator

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its seems there is no testbench in the project . You are invoking simulator on your top level.

1. Add the test bench and drive all the input signals correctly . I can see input signal are toggle here that mean you are not driving your inputs correctly .

2 . You need to make sure your top level rightly instantiate in the test bench

this is good site where you will get some examples .

http://esd.cs.ucr.edu/labs/tutorial/
Thanks and Regards
Balkrishan
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Xilinx Employee
Xilinx Employee
10,276 Views
Registered: ‎05-20-2015

Re: 2014.3 VIVADO Webpack Simulator

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Hi @serge1973,

You can use the following simple test bench and check the results.

 


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity test_top_ff is
end test_top_ff;

architecture Behavioral of test_top_ff is

component dff_hw is
port (clk, rst, d: in  std_logic;
                q: out std_logic);
end component;


signal clk,rst,d,q : std_logic;
constant clk_period : time:= 10 ns;

begin
 uut : dff_hw port map
      (clk => clk,
       rst => rst,
       d => d,
       q => q
       );
      
clk_process : process
     begin
     clk <= '0';
     wait for clk_period/2;
     clk<= '1';
     wait for clk_period/2;
 end process;
 
 stimulus_process : process
     begin
     wait for 3 ns;
     rst <= '1';
     wait for 5 ns;
     rst <= '0';
    
     d <= '1';
     wait for 7 ns;
     d <='0';
     wait for 5 ns;
    
     rst<= '1';
     wait for 10ns;
    
     d<= '1';
     wait for 5 ns;
     d<= '0';
     wait for 5 ns;
    
     rst<='0';
     wait for 12 ns;
     d<= '1';
     wait for 10 ns;
     rst<= '1';
     d<= '0';
 end process;
      
 end Behavioral;

 

 

Thanks,

Rajesh

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Observer
Observer
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Registered: ‎09-13-2015

Re: 2014.3 VIVADO Webpack Simulator

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Hi @rajeshtu,

Thanks it's doing something. I'm new to this so I'd like to ask few questions:

 What's test bench? Is the test bench run simultaneously with my code above? Or is this embedded in my DFF code?

THanks!

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Observer
Observer
10,271 Views
Registered: ‎09-13-2015

Re: 2014.3 VIVADO Webpack Simulator

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Hi @vuppala,
I'm new to this software so I didn't know about testbench?
I tried to force the clock through some options in vivado but that didn't yield any result. Is toggling the clock done through the code?
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Observer
Observer
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Registered: ‎09-13-2015

Re: 2014.3 VIVADO Webpack Simulator

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hi @balris.
Is the test bench (I assume some type of code) is ran concurrently with my code above?
What do you mean by top level rightly instantiate in the test bench?
Thanks for the link
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Xilinx Employee
Xilinx Employee
10,269 Views
Registered: ‎05-20-2015

Re: 2014.3 VIVADO Webpack Simulator

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Hi,
Go through this link for the basic understanding of test bench.
http://www.xilinx.com/itp/xilinx10/isehelp/ise_c_simulation_test_bench.htm

Thanks,
Rajesh

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Observer
Observer
10,251 Views
Registered: ‎09-13-2015

Re: 2014.3 VIVADO Webpack Simulator

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 I think I got it to work but I have question regarding q (output). I'd expect it at some point to be q <= d when clk = 1. It does not seem to happen. 

Here's my test bench code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity hw_dff_tb is
end hw_dff_tb;

--------------------------------------------------------


architecture Behavioral of hw_dff_tb is
-- Component Declaration for the Unit Under Test (UUT)
component hw_dff is
port(clk, rst, d: in std_logic;
q: out std_logic);
end component;


--Inputs
signal hw_dff_tb_clk : std_logic := '0';
signal hw_dff_tb_rst : std_logic := '0';
signal hw_dff_tb_d : std_logic;
signal hw_dff_tb_q : std_logic;

--Outputs

-- Clock period definitions
constant hw_dff_tb_clock_period : time := 10ns;

begin
-- Instantiate the Unit Under Test (UUT)
uut : hw_dff port map

(clk => hw_dff_tb_clk,
rst => hw_dff_tb_rst,
d => hw_dff_tb_d,
q => hw_dff_tb_q);

-- Clock process definitions

clock_process : process
begin
hw_dff_tb_clk <= '0';
wait for hw_dff_tb_clock_period/2;
hw_dff_tb_clk <= '1';
wait for hw_dff_tb_clock_period/2;
end process;

-- Stimulus process

stim_proc : process
begin
-- hold reset state for 100us.

hw_dff_tb_rst <= '1';
hw_dff_tb_d <= '0'; --Change from 1 to 0
wait for hw_dff_tb_clock_period*2;
hw_dff_tb_rst <= '0';
wait for hw_dff_tb_clock_period*1;
hw_dff_tb_d <= '1';
wait for hw_dff_tb_clock_period*1;
hw_dff_tb_d<= '0';
--wait;
end process;
end Behavioral;

waveform1.JPG
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Xilinx Employee
Xilinx Employee
9,300 Views
Registered: ‎05-20-2015

Re: 2014.3 VIVADO Webpack Simulator

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Hi  @serge1973,

The component name must be 'dff_hw' whereas you have defined it 'hw_dff' by mistake.

Please change it and check the result.

 

Thanks,
Rajesh

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Observer
Observer
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Registered: ‎09-13-2015

Re: 2014.3 VIVADO Webpack Simulator

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Hi @rajeshtu,

Thank you for getting back to me. I changed component from hw_dff to dff_hw and that didn't work.  I got error.

To clarify, I have file named hw_dff.vhd which contains the flip-flop code and here's the copy:

------------------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity dff_hw is
 port (clk : in std_logic;
 rst : in std_logic;
 d : in std_logic;
 q : out std_logic);
end entity;
architecture behavioral of dff_hw is
begin
 process (clk, rst)
 begin
   if (rst = '1') then
      q <= '0';
   elsif (clk'event and clk = '1') then
      q <= d;
   end if;
 end process;
end architecture;

--------------------------------------------------------------------------------------------

 

So I used the code that I posted earlier as the test bench but for some reason the output doesn't change on the rising of the clock.

Also, on the orignal test bench that I am asked to fix and simulate has the following information on the signals which I removed since I could not run the simulation with inputs configured as below. I'm wondering if that's where std_logic_vector needs to be

 

 

 --Inputs signal hw_dff_tb_clk : std_logic := '0';

signal hw_dff_tb_rst : std_logic := '0';

signal hw_dff_tb_d : std_logic_vector(7 downto 0) := (others => '0');

--Outputs

signal hw_dff_tb_q : std_logic_vector(7 downto 0);

 

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Observer
Observer
9,291 Views
Registered: ‎09-13-2015

Re: 2014.3 VIVADO Webpack Simulator

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Sorry hear is the right code for hw_dff.vhd:

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity hw_dff is
port (clk : in std_logic;
rst : in std_logic;
d : in std_logic;
q : out std_logic);
end entity;
architecture behavioral of hw_dff is
begin
process (clk, rst)
begin
if (rst = '1') then
q <= '0';
elsif (clk'event and clk = '1') then
q <= d;
end if;
end process;
end architecture;
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Xilinx Employee
Xilinx Employee
9,277 Views
Registered: ‎05-20-2015

Re: 2014.3 VIVADO Webpack Simulator

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Hi @serge1973,

 

Firstly, no need to declare the signals hw_dff_tb_d and hw_dff_tb_q as 8 bit bus (std_logic_vector(7 donwto 0)) because those are defined as single bit (std_logic) in the design.

Please use the attached code and test bench which is working fine at my end.

Here's the waveform.

 

waveform_ff.PNG

 

Thanks,
Rajesh

-----------------------------------------------------------------------------------------------------

Please mark the answer as accepted solution if in case it helped resolving your query.

Give Kudos to the post in case it guided to the solution.

 

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Observer
Observer
18,843 Views
Registered: ‎09-13-2015

Re: 2014.3 VIVADO Webpack Simulator

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Hi @rajeshtu

Works swimmingly! Thanks a lot for your help.

View solution in original post

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Moderator
Moderator
9,239 Views
Registered: ‎04-17-2011

Re: 2014.3 VIVADO Webpack Simulator

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@serge1973 : As a good Forums Practice, it is suggested to mark the post which helped you as an Accepted Solution, so that anyone who visits this thread would know which post helped you (rather than marking your reply as an Accepted Solution). You can still change the marking and add it to the post which actually helped you. Thanks.
Regards,
Debraj
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