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urburb
Observer
Observer
2,364 Views
Registered: ‎10-21-2009

2017.2: Error compiling verilog IP libs with Modelsim - space in Win 7 user name

When using the 'Compile Simulation Libraries' tool in Vivado 2017.2 to compile the IP libraries using Modelsim 10.6c, all the IP libraries generate an error when compiling for verilog. The base (non-IP) libraries (unisim, simprim,...) compile without error for verilog.

 

The difference between the Modelsim commands for the base libraries and IP is the addition of an include path for IP libraries. It appears that Vivado places some verilog header files in the following path:

 

C:\Users\<username>\AppData\Roaming\Xilinx\Vivado\.cxl.ip/incl

 

In my case my username ("first last") has a space in it, thus the include path contains a space. The verilog compilation error appears to be a result of compile_simlib not quoting the include path when creating the modelsim compilation command. The following shows the results of issuing one of the verilog library compilation commands (copied from log) in a cmd window. Without escaping the include path a compilation error occurs and points to a bad include path. Quoting the include path allows the library to compile without error.

 

Compiling with verbatim comp_simlib generated command

'No such file or directory' error is generated.

 

C:\Users\Paul Urbanus\C:\Users\Paul Urbanus\AppData\Roaming\Xilinx\Vivado>C:\modeltech_pe_10.6c\win32pe/vlog  -64 +incdir+C:\Users\Paul Urbanus\AppData\Roaming\Xilinx\Vivado\.cxl.ip/incl -work axis_protocol_checker_v1_1_13 -f C:\Xilinx\Vivado\2017.2\mti/axis_protocol_checker_v1_1_13/.cxl.verilog.axis_protocol_checker_v1_1_13.axis_protocol_checker_v1_1_13.nt64.cmf
** Warning: (vlog-159) Mode option -64 is not supported in this context and will be ignored.
Model Technology ModelSim PE vlog 10.6c Compiler 2017.07 Jul 26 2017
Start time: 06:53:49 on Dec 06,2017
vlog -64 "+incdir+C:\Users\Paul" Urbanus\AppData\Roaming\Xilinx\Vivado\.cxl.ip/incl -work axis_protocol_checker_v1_1_13 -f C:\Xilinx\Vivado\2017.2\mti/axis_protocol_checker_v1_1_13/.cxl.verilog.axis_protocol_checker_v1_1_13.axis_protocol_checker_v1_1_13.nt64.cmf
** Error: (vlog-7) Failed to open design unit file "Urbanus\AppData\Roaming\Xilinx\Vivado\.cxl.ip/incl" in read mode.
No such file or directory. (errno = ENOENT)
End time: 06:53:49 on Dec 06,2017, Elapsed time: 0:00:00
Errors: 1, Warnings: 1

 

Compiling with modified comp_simlib generated command

Note that the include path has been delimited with quotes and the compilation is successful.

C:\Users\Paul Urbanus\AppData\Roaming\Xilinx\Vivado>C:\modeltech_pe_10.6c\win32pe/vlog  -64 +incdir+"C:\Users\Paul Urbanus\AppData\Roaming\Xilinx\Vivado\.cxl.ip/incl" -work axis_protocol_checker_v1_1_13 -f C:\Xilinx\Vivado\2017.2\mti/axis_protocol_checker_v1_1_13/.cxl.verilog.axis_protocol_checker_v1_1_13.axis_protocol_checker_v1_1_13.nt64.cmf
** Warning: (vlog-159) Mode option -64 is not supported in this context and will be ignored.
Model Technology ModelSim PE vlog 10.6c Compiler 2017.07 Jul 26 2017
Start time: 06:54:14 on Dec 06,2017
vlog -64 "+incdir+C:\Users\Paul Urbanus\AppData\Roaming\Xilinx\Vivado\.cxl.ip/incl" -work axis_protocol_checker_v1_1_13 -f C:\Xilinx\Vivado\2017.2\mti/axis_protocol_checker_v1_1_13/.cxl.verilog.axis_protocol_checker_v1_1_13.axis_protocol_checker_v1_1_13.nt64.cmf
-- Compiling module axis_protocol_checker_v1_1_13_asr_inline
-- Compiling module axis_protocol_checker_v1_1_13_reporter
-- Compiling module axis_protocol_checker_v1_1_13_top

Top level modules:
        axis_protocol_checker_v1_1_13_top
End time: 06:54:15 on Dec 06,2017, Elapsed time: 0:00:01
Errors: 0, Warnings: 1

 

How can I get compile_simlib to compile the IP libraries for verilog without error? If I have to do so I could write a script extract the commands from the compile_simlib log file and quote the include path. But I would prefer a cleaner solution.

 

I didn't find any answer record that addressed this. Unless I've done something incorrectly (other than selecting a bad user name years ago), this appears to be a bug in compile_simlib, so it would be nice to have it reported.

 

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3 Replies
amaccre
Moderator
Moderator
2,346 Views
Registered: ‎04-24-2013

Hi @urburb,

 

Can you try the following, which may help.

 

You should be able to choose where you want the compiled libraries stored.

 

If you are using the GUI to do the compilation then just set this in the Compiled library location.

 

In this case I have put them on my H: drive but you can choose any location that suits.

 

If using the tcl console to compile them then use the -directory switch to select the location e.g.

 

compile_simlib -simulator modelsim -directory c:\compiled_libs

 

Capture.PNG

 

Let me know if this helps or if you need further assistance.

 

BTW there is an Answer Record about spaces in paths and compatibility with Vivado which I will try and find again.

 

Best Regards
Aidan

 

 

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urburb
Observer
Observer
2,338 Views
Registered: ‎10-21-2009

Hi Adrian,

 

The issue isn't with the destination of the compiled libraries, which I believe is what you addressed in your reply. The libraries are being compiled to the following location, which has no spaces.

 

C:\Xilinx\Vivado\2017.2\mti

 

This issue is that the Vivado compile_simlib tool appears to place the verilog headers in the user Appdata\Roaming path, as described in my original post and shown below. And my user name contains a space, as it has the form, 'first last'.

 

C:\Users\<username>\AppData\Roaming\Xilinx\Vivado\.cxl.ip/incl

 

Spaces are argument delimiters on the command line unless the space-containing argument is delimited with quotes. As the original post verified, quoting the header path in the Modelsim command resulted in the library being compiled successfully.

 

I'm not aware of any way to change this verilog header path, as it seems to be part of the way the compile_simlib tool works. I was hoping there was a way to change this. In the end, this is appears to me to be a bug in that compile_simlib installs the verilog headers in a path known to have spaces, yet doesn't quote the path when creating the modelsim command to compile the IP libraries for verilog.

 

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graces
Moderator
Moderator
2,316 Views
Registered: ‎07-16-2008

Please try to run compile_simlib from a different path.

e.g.

  1. Type cmd in Start menu to open a command prompt.
  2. Set up Xilinx environment by running: C:\Xilinx\Vivado\2017.2\settings64.bat. Replace the path with the Vivado install directory on your machine.
  3. Change directory to anywhere that doesn't have space in path name (cd C:\compile_viv_lib).
  4. From that directory, enter Vivado Tcl mode by running: vivado -mode tcl
  5. Run tcl command compile_simlib. You can specify the options like in your previous run.

 

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