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Observer ronagyl_adi
Observer
929 Views
Registered: ‎05-11-2018

2018.2 SystemVerilog randomization

 

The below example is taken from LRM 18.3 Concepts and usage.

The code should generate word aligned addresses but sadly in Vivado 2018.2 it produces all zeros ...

In 2017.4 worked well.

 

class Bus;
    rand bit [15:0] addr;
    rand bit [31:0] data;
    constraint  word_align {addr[1:0] == 2'b0;}
endclass

module test2();
        
    Bus bus = new;
    
    initial
        repeat (50) begin
            if ( bus.randomize() == 1 )
                $display ("addr = %16h data = %h", bus.addr, bus.data);
            else
                $display ("Randomization failed.");
        end
    
endmodule

Produced output:

addr = 0000000000000000 data = 37b1b363
addr = 0000000000000000 data = f9d18e47
addr = 0000000000000000 data = f25cf357
addr = 0000000000000000 data = 938318f0
addr = 0000000000000000 data = c20bc5d0
addr = 0000000000000000 data = dd783a85

....

 

 

 

Thanks

 

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3 Replies
Xilinx Employee
Xilinx Employee
926 Views
Registered: ‎08-10-2015

Re: 2018.2 SystemVerilog randomization

hi @ronagyl_adi,

 

Randomization is not working if we write constraint to set value '0' to part select of random variable. If we set constraint for any other value other than zero, it is working. Issue reported to the factory.

 

 

Thanks,

Sunilkumar

Highlighted
Observer ronagyl_adi
Observer
865 Views
Registered: ‎05-11-2018

Re: 2018.2 SystemVerilog randomization

Hi @sunilku

 

From what I see the randomization does not work at all in case of part selections.

 

when I set  constraint  word_align {addr[3:0] == 4'd8;} the rest of the bits are not randomized, the whole addr gets the value of 8 just like in case of zero;

 

when I set  constraint  word_align {addr[3:0] == {1'b1,3'b0};} randomization fails, this seems to be another issue.

 

 

Please can you detail what you mean by: "If we set constraint for any other value other than zero, it is working."

 

Thanks,

Laszlo

 

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Xilinx Employee
Xilinx Employee
859 Views
Registered: ‎08-10-2015

Re: 2018.2 SystemVerilog randomization

Hi @ronagyl_adi,

 

I do see the same behavior for the part select of random variable in constraint block. I suggest you not to use part-select until this issue is fixed.

 

 

Thanks,

Sunilkumar  

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