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sourissahu
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Registered: ‎01-23-2020

64 bit Floating point adder using IP core not working.

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mine.v

 

timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02/18/2021 04:39:11 PM
// Design Name:
// Module Name: mine
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module mine(input aclk,s_axis_a_tvalid,s_axis_b_tvalid,m_axis_result_tready,
output s_axis_a_tready,s_axis_b_tready,m_axis_result_tvalid,
input wire [63:0] s_axis_a_tdata, s_axis_b_tdata,
output wire [63:0] m_axis_result_tdata);

 

 

floating_point_Add64 fp_64 (
.aclk(aclk), // input wire aclk
.s_axis_a_tvalid(s_axis_a_tvalid), // input wire s_axis_a_tvalid
.s_axis_a_tready(s_axis_a_tready), // output wire s_axis_a_tready
.s_axis_a_tdata(s_axis_a_tdata), // input wire [63 : 0] s_axis_a_tdata
.s_axis_b_tvalid(s_axis_b_tvalid), // input wire s_axis_b_tvalid
.s_axis_b_tready(s_axis_b_tready), // output wire s_axis_b_tready
.s_axis_b_tdata(s_axis_b_tdata), // input wire [63 : 0] s_axis_b_tdata
.m_axis_result_tvalid(m_axis_result_tvalid), // output wire m_axis_result_tvalid
.m_axis_result_tready(m_axis_result_tready), // input wire m_axis_result_tready
.m_axis_result_tdata(m_axis_result_tdata) // output wire [63 : 0] m_axis_result_tdata
);


endmodule

mine_tb.v

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02/18/2021 04:53:30 PM
// Design Name:
// Module Name: mine_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module mine_tb();
reg aclk,s_axis_a_tvalid,s_axis_b_tvalid,m_axis_result_tready;
wire s_axis_a_tready,s_axis_b_tready,m_axis_result_tvalid;
reg [63:0] s_axis_a_tdata, s_axis_b_tdata;
wire [63:0] m_axis_result_tdata;

mine mm1(.aclk(aclk), // input wire aclk
.s_axis_a_tvalid(s_axis_a_tvalid), // input wire s_axis_a_tvalid
.s_axis_a_tready(s_axis_a_tready), // output wire s_axis_a_tready
.s_axis_a_tdata(s_axis_a_tdata), // input wire [63 : 0] s_axis_a_tdata
.s_axis_b_tvalid(s_axis_b_tvalid), // input wire s_axis_b_tvalid
.s_axis_b_tready(s_axis_b_tready), // output wire s_axis_b_tready
.s_axis_b_tdata(s_axis_b_tdata), // input wire [63 : 0] s_axis_b_tdata
.m_axis_result_tvalid(m_axis_result_tvalid), // output wire m_axis_result_tvalid
.m_axis_result_tready(m_axis_result_tready), // input wire m_axis_result_tready
.m_axis_result_tdata(m_axis_result_tdata) // output wire [63 : 0] m_axis_result_tdata);
);

always
begin
#10 aclk=~aclk;
end

initial
begin
aclk=1;
s_axis_a_tvalid=0;
s_axis_b_tvalid=0;
m_axis_result_tready=0;
s_axis_a_tdata=0;
s_axis_b_tdata=0;
#100
s_axis_a_tvalid=1;
s_axis_b_tvalid=1;
#100
m_axis_result_tready=1;
s_axis_a_tdata=64'b0100;
s_axis_b_tdata=64'b1000;
#400
s_axis_a_tdata=64'b0101;
s_axis_b_tdata=64'b1010;
#400
s_axis_a_tdata=64'b0101;
s_axis_b_tdata=64'b1011;
#400
s_axis_a_tdata=64'b0110;
s_axis_b_tdata=64'b1100;
#400
s_axis_a_tdata=64'b0111;
s_axis_b_tdata=64'b1111;
end

endmodule

 

sourissahu_1-1613800617148.png

I am new in this field. Please tell me what is the fault? why the output is not coming? why output 4503599627370496 is coming without any input? 

 

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joancab
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Registered: ‎05-11-2015

In theory it should work with your values: 0x10 understood as a float is 2.24207754292e-44, and 0x12 is 2.52233723578e-44, so the sum is 4.76441478E-44 that as integer is 0x22. What might happen is that the core is rounding that small number to zero.

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drjohnsmith
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Registered: ‎07-09-2009

sorry , cant see that small a picture on the tablet,

 way to debug this is to start at the top of the simulation file, and check the inputs ,

         are they as per data sheet for the core, is reset the correct way up ? 

            for instance, are any of the inputs "unknown" ?

              have you run the simulation long enough ?

then dive down into the simulation , check further inputs, 

    you will find that some where the input s are not correct

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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joancab
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@sourissahu 

Your module 'mine' just wraps another module called floating_point_Add64. What's in there?

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sourissahu
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floating_point_Add64 fp_64 (
.aclk(aclk), // input wire aclk
.s_axis_a_tvalid(s_axis_a_tvalid), // input wire s_axis_a_tvalid
.s_axis_a_tready(s_axis_a_tready), // output wire s_axis_a_tready
.s_axis_a_tdata(s_axis_a_tdata), // input wire [63 : 0] s_axis_a_tdata
.s_axis_b_tvalid(s_axis_b_tvalid), // input wire s_axis_b_tvalid
.s_axis_b_tready(s_axis_b_tready), // output wire s_axis_b_tready
.s_axis_b_tdata(s_axis_b_tdata), // input wire [63 : 0] s_axis_b_tdata
.m_axis_result_tvalid(m_axis_result_tvalid), // output wire m_axis_result_tvalid
.m_axis_result_tready(m_axis_result_tready), // input wire m_axis_result_tready
.m_axis_result_tdata(m_axis_result_tdata) // output wire [63 : 0] m_axis_result_tdata
);

============================================================================

This is floating-point 64 bit add IP taken from the IP catalog. Copied and pasted from .veo file.

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sourissahu
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This floating-point IP is taken from IP catalog. What I have understood  

.s_axis_a_tvalid, s_axis_b_tvalid,  should be high to validate a and b data and  .m_axis_result_tready should be high to get the output. 

if .s_axis_a_tvalid, s_axis_b_tvalid, both high,(i/p) 

            if s_axis_a_tready and s_axis_b_tready is high(o/p)

                                          s_axis_a_tdata and s_axis_b_tdata valid.(i/p)

now 

if m_axis_result_tready high(i/p)

     if m_axis_result_tvalid high(o/p)

           I should get the result of addition.

 keeping s_axis_a_tvalid,s_axis_b_tvalid and m_axis_result_tready high I am giving data. But there is no change in output.

 

I need to see some working examples. But I haven't found one.  I need to know the way I understand the inputs and outputs. They are correct or not.

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joancab
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The way I use the IP catalog is to drop the cores into a block diagram. How did you generate that veo file?

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joancab
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If you want to test an IP from the catalogue, I'd suggest you create a block diagram, add the IP there, connect all pins to ports (you can just select the whole block and right click 'make external'), create an HDL wrapper for that diagram and write your testbench for the wrapper.

joancab_0-1613986794578.png

 

sourissahu
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Registered: ‎01-23-2020

Thanks for this information.

I have tried but still, there is no change in output.

my block diagram is:

sourissahu_0-1614019943000.png

ignore the name floating_point_Add64 should be Add32 as this time I have considering 32 bit.

wrapper

//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
//Date : Mon Feb 22 22:15:20 2021
//Host : souris-pc running 64-bit major release (build 9200)
//Command : generate_target design_1_wrapper.bd
//Design : design_1_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

module design_1_wrapper
(aclk_0,
m_axis_result_tdata_0,
m_axis_result_tready_0,
m_axis_result_tvalid_0,
s_axis_a_tdata_0,
s_axis_a_tready_0,
s_axis_a_tvalid_0,
s_axis_b_tdata_0,
s_axis_b_tready_0,
s_axis_b_tvalid_0);
input aclk_0;
output [31:0]m_axis_result_tdata_0;
input m_axis_result_tready_0;
output m_axis_result_tvalid_0;
input [31:0]s_axis_a_tdata_0;
output s_axis_a_tready_0;
input s_axis_a_tvalid_0;
input [31:0]s_axis_b_tdata_0;
output s_axis_b_tready_0;
input s_axis_b_tvalid_0;

wire aclk_0;
wire [31:0]m_axis_result_tdata_0;
wire m_axis_result_tready_0;
wire m_axis_result_tvalid_0;
wire [31:0]s_axis_a_tdata_0;
wire s_axis_a_tready_0;
wire s_axis_a_tvalid_0;
wire [31:0]s_axis_b_tdata_0;
wire s_axis_b_tready_0;
wire s_axis_b_tvalid_0;

design_1 design_1_i
(.aclk_0(aclk_0),
.m_axis_result_tdata_0(m_axis_result_tdata_0),
.m_axis_result_tready_0(m_axis_result_tready_0),
.m_axis_result_tvalid_0(m_axis_result_tvalid_0),
.s_axis_a_tdata_0(s_axis_a_tdata_0),
.s_axis_a_tready_0(s_axis_a_tready_0),
.s_axis_a_tvalid_0(s_axis_a_tvalid_0),
.s_axis_b_tdata_0(s_axis_b_tdata_0),
.s_axis_b_tready_0(s_axis_b_tready_0),
.s_axis_b_tvalid_0(s_axis_b_tvalid_0));
endmodule

Testbench:

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02/22/2021 10:17:04 PM
// Design Name:
// Module Name: Add32tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module Add32tb(

);
reg aclk_0;
wire [31:0]m_axis_result_tdata_0;
reg m_axis_result_tready_0;
wire m_axis_result_tvalid_0;
reg [31:0]s_axis_a_tdata_0;
wire s_axis_a_tready_0;
reg s_axis_a_tvalid_0;
reg [31:0]s_axis_b_tdata_0;
wire s_axis_b_tready_0;
reg s_axis_b_tvalid_0;
design_1_wrapper m1
(.aclk_0(aclk_0),
.m_axis_result_tdata_0(m_axis_result_tdata_0),
.m_axis_result_tready_0(m_axis_result_tready_0),
.m_axis_result_tvalid_0(m_axis_result_tvalid_0),
.s_axis_a_tdata_0(s_axis_a_tdata_0),
.s_axis_a_tready_0(s_axis_a_tready_0),
.s_axis_a_tvalid_0(s_axis_a_tvalid_0),
.s_axis_b_tdata_0(s_axis_b_tdata_0),
.s_axis_b_tready_0(s_axis_b_tready_0),
.s_axis_b_tvalid_0(s_axis_b_tvalid_0));

initial begin aclk_0=1; end
always begin #10 aclk_0= ~aclk_0; end
initial
begin
m_axis_result_tready_0=0;
s_axis_a_tdata_0=0;
s_axis_a_tvalid_0=0;
s_axis_b_tdata_0=0;
s_axis_b_tvalid_0=0;

#100
m_axis_result_tready_0=1;
s_axis_a_tdata_0=10;
s_axis_a_tvalid_0=1;
s_axis_b_tdata_0=12;
s_axis_b_tvalid_0=1;
#100
m_axis_result_tready_0=1;
s_axis_a_tdata_0=23;
s_axis_a_tvalid_0=1;
s_axis_b_tdata_0=34;
s_axis_b_tvalid_0=1;
end
endmodule

simulated wave:

sourissahu_1-1614020273923.png

There is no effect on output. It remains same i.e. 0.  

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joancab
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Your problem is you are entering values as integers but there is no automatic conversion to float. You need to use a conversor to IEEE754 float format, for example this: 

IEEE-754 Floating Point Converter (h-schmidt.net)

I redid your design and could add 1+2, 2+2 and 2+3. In the simulation screen you can right click a signal and select the radix as float point single, at least it makes the conversion back for you.

joancab_0-1614024195021.png

There is something I don't fully understand, the output (looking at tvalid) seems to be 4, 4, 5 and there is that 3 at the output without tvalid.

It needs a bit more research, but hopefully this keeps you cracking on.

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joancab
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In theory it should work with your values: 0x10 understood as a float is 2.24207754292e-44, and 0x12 is 2.52233723578e-44, so the sum is 4.76441478E-44 that as integer is 0x22. What might happen is that the core is rounding that small number to zero.

View solution in original post

sourissahu
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Registered: ‎01-23-2020

Thank you

 

 

 

 

 

 This was really helpful. I was not understanding where is the fault.(Y)

joancab
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Registered: ‎05-11-2015

From Single-precision floating-point format - Wikipedia

1.1754943508 × 10−38 is the "smallest positive normal number" but 1.4012984643 × 10−45 is the "smallest positive subnormal number". I suppose "subnormal" means invalid and rounded to zero.

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sourissahu
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I have one more question. 

Suppose I need a Verilog file of very complex logic. For that, I have written 26 .v files of submodules. Each of them required multiple floating point IP such as adder, subtract, multiply, square root etc. etc. Also, I don't know in which fashion they will be connected physically. Only I can write a behavioral model with all 26 submodules. 

So in this case I cannot build a block diagram. I have to make own IP from verilog files and logicIPs. Then I can make a block diagram with my IP and processor.

How to use LogicIPs here? from Ip catalog ?

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joancab
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Best to start a new post, they are free

You can drop hdl files into a block diagram, they become blocks that you can connect to others and to catalogue IPs.

Or, you can generate a wrapper from a block diagram and instantiate it in another HDL file.