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bitwiselannon
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Registered: ‎02-08-2013

7-series IDELAY simulation delay insertion

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I have a behavioural simulation working, and use some IDELAY blocks in my code. Delay value is set to 0 and the delay_cnt value out is 0. I am seeing a default delay through this module of 600ps in simulation??

 

In the DC switching characteristics for the Kintex-7 (DS182)  T.IDDO_IDATAIN is the propagation delay through IDELAY just says to use TRACE to get it's value. Can I assume the simulation model is has an accurate delay built in? Seems like quite a long delay.

 

 

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graces
Moderator
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Registered: ‎07-16-2008
Device
Input Side Delay
Output Side Delay
7-Series IDELAYE2=600 ps ODELAYE= 600 ps
Virtex-6 IODELAYE1=144 ps IODELAYE1=144 ps
Spartan-6 IODELAY2=100 ps IODELAY2=no inital delay modelled
Virtex-5 IODELAY=no inital delay modelled IODELAY=no inital delay modelled
Virtex-4 IDELAY=no inital delay modelled No output delay
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vuppala
Xilinx Employee
Xilinx Employee
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Registered: ‎04-16-2012
Hi,

Check the sdf file being generated in the <project_directory>/netgen/translate or map or par/.sdf for delays.

Thanks
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bitwiselannon
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Sorry, I forgot to mention I'm using Planahead 14.6 and Isim for the behavoural sim. 

 

I did find a sdf file in the .sim directory for my testbench but I don't think it shows built in delays of 600ps. I think the sdf file is used in acurate timing driven simulation where I suspect in my Behavioural simulation, the behavioural simulation model must have something like: 'O <= I after 600 ps' to model an inherent propagation delay.

 

sdf contents after an IDELAY2 search:

 

(CELL (CELLTYPE "X_IDELAYE2")
(INSTANCE ADC_iface\/Deskew_channels\[4\]\.Adc_bit_delay_inst)
(DELAY
(ABSOLUTE
(PORT C ( 0 )( 0 ))
(PORT CE ( 0 )( 0 ))
(PORT CINVCTRL ( 0 )( 0 ))
(PORT CNTVALUEIN[0] ( 0 )( 0 ))
(PORT CNTVALUEIN[1] ( 0 )( 0 ))
(PORT CNTVALUEIN[2] ( 0 )( 0 ))
(PORT CNTVALUEIN[3] ( 0 )( 0 ))
(PORT CNTVALUEIN[4] ( 0 )( 0 ))
(PORT DATAIN ( 0 )( 0 ))
(PORT IDATAIN ( 0 )( 0 ))
(PORT INC ( 0 )( 0 ))
(PORT LD ( 0 )( 0 ))
(PORT LDPIPEEN ( 0 )( 0 ))
(PORT REGRST ( 0 )( 0 ))
(IOPATH C CNTVALUEOUT[4:0] (291:577:577)(291:577:577))
(IOPATH CINVCTRL CNTVALUEOUT[4:0] (327:653:653)(327:653:653))
)
)
(TIMINGCHECK
(PERIOD (posedge C) (2000))
(SETUPHOLD(posedge CE) (posedge C) (27:133:133)(55:112:112))
(SETUPHOLD(negedge CE) (posedge C) (27:133:133)(55:112:112))
(SETUPHOLD(posedge INC) (posedge C) (56:115:115)(45:157:157))
(SETUPHOLD(negedge INC) (posedge C) (56:115:115)(45:157:157))
(SETUPHOLD(posedge LD) (posedge C) (47:78:78)(38:99:99))
(SETUPHOLD(negedge LD) (posedge C) (47:78:78)(38:99:99))
)
)

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graces
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Registered: ‎07-16-2008

Yes, the 600 ps is intentionally added to simulaiton model to model the intrinsic delay through IODELAY.

Check out  this AR.

http://www.xilinx.com/support/answers/42133.htm

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graces
Moderator
Moderator
8,609 Views
Registered: ‎07-16-2008
Device
Input Side Delay
Output Side Delay
7-Series IDELAYE2=600 ps ODELAYE= 600 ps
Virtex-6 IODELAYE1=144 ps IODELAYE1=144 ps
Spartan-6 IODELAY2=100 ps IODELAY2=no inital delay modelled
Virtex-5 IODELAY=no inital delay modelled IODELAY=no inital delay modelled
Virtex-4 IDELAY=no inital delay modelled No output delay
-----------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs.
-----------------------------------------------------------------------------------------------------------------------

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bitwiselannon
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Registered: ‎02-08-2013

Wow, quite a delay for the pleasure of being able to tweak up to 2ns!

 

Thanks for that. I can't see why they don't have that in the DC switching characteristics data sheet.

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