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Anonymous
Not applicable
8,265 Views

A long time to wait sub-compile when use xsim(vivado 2012.4 )

My design is operate on vivado 2012.4. 

In RTL code there are ddr3 , fifos , axi-interconnetors that generated in vivado.

simulation sequecen is ->

1, simulation settings is defult

2, click [Run Simulation] in vivado

 

after this , tools begin to complie library .the xelab.log is shown as below

++++++++++++++++++++++++++++++++++++++++++++++++++++++++

Compiling module work.FPGA_K7_TOP
Compiling module work.c0_ddr3_model_default
Compiling module work.c1_ddr3_model_default
Compiling module work.c2_ddr3_model_default
Compiling module work.c3_ddr3_model_default
Compiling module work.TB_TOP
Compiling module work.glbl
Waiting for 279 sub-compilation(s) to finish...

++++++++++++++++++++++++++++++++++++++++++++++++++++++++

From this status to start xsim about  40 minutes, it's too long to simuate my designs

 

After investigation, I found that the number of sun-compilation is increment when used ip-core in design ,that means long time to wait . could anyone tell me the reason ?

 

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19 Replies
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Visitor
Visitor
8,051 Views
Registered: ‎07-02-2013

Hi,

I face the same problem under vivado 2013.2. Did you found a reason and solution ?

Regards


@Anonymous wrote:

My design is operate on vivado 2012.4. 

In RTL code there are ddr3 , fifos , axi-interconnetors that generated in vivado.

simulation sequecen is ->

1, simulation settings is defult

2, click [Run Simulation] in vivado

 

after this , tools begin to complie library .the xelab.log is shown as below

++++++++++++++++++++++++++++++++++++++++++++++++++++++++

Compiling module work.FPGA_K7_TOP
Compiling module work.c0_ddr3_model_default
Compiling module work.c1_ddr3_model_default
Compiling module work.c2_ddr3_model_default
Compiling module work.c3_ddr3_model_default
Compiling module work.TB_TOP
Compiling module work.glbl
Waiting for 279 sub-compilation(s) to finish...

++++++++++++++++++++++++++++++++++++++++++++++++++++++++

From this status to start xsim about  40 minutes, it's too long to simuate my designs

 

After investigation, I found that the number of sun-compilation is increment when used ip-core in design ,that means long time to wait . could anyone tell me the reason ?

 




 

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Xilinx Employee
Xilinx Employee
8,045 Views
Registered: ‎04-16-2012

Hi,

 

Which OS are you using?

And the RAM installed on the machine?

 

Thanks.

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Participant
Participant
8,028 Views
Registered: ‎08-06-2013

I have the same issue. I am using AXI4 ddr2 memory interface (with FFM simulation model),  AXI4 interconnect and my own RTL logic.

Running Vivado 2013.2 on Windows 7 64-bit with 8GB, i7-2600 CPU, 3.8GHz.

 

Every time I “Run Simulation” the IP cores and the full design are recompiled even though they have not been changed. Is there any way to avoid recompilation for cores and logic blocks that have not been changed?

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Moderator
Moderator
8,018 Views
Registered: ‎04-17-2011

Hello Everyone,

There is a roadmap plan of re-incorporating -incremental switch in future which would prevent re-compilation of already compiled modules. It would be similar to -Mupdate in VCS or -incr in Modelsim.

Currently it is not possible to prevent recompilation of files while re-running simulation. Our Development team is working on the same.
Regards,
Debraj
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Participant
Participant
8,011 Views
Registered: ‎08-06-2013

Thanks Debraj,

 

It would be great if you could update the thread when this feature is available.

It already takes 15 minutes to compile my current design and it is only a small part of the whole design.

Unfortunately test benching smaller blocks is not an option at this stage.

 

Regards,

Vlad

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Moderator
Moderator
8,007 Views
Registered: ‎04-17-2011

Sure Vlad, I would keep track of this and update this post.
Regards,
Debraj
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Scholar
Scholar
7,947 Views
Registered: ‎09-05-2011

Hi,

 

It is in the pipeline:

 

http://www.xilinx.com/support/answers/57239.htm

 

Regards,

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Observer
Observer
7,521 Views
Registered: ‎03-20-2012

Hi,

 

Just wondering if any progress has been made here? I am still experience long pre compile times in 2013.4 . Its a real bottleneck in doing any IP core designs on this platform.

 

Regards,

Jon.

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Moderator
Moderator
7,514 Views
Registered: ‎04-17-2011

This is not in for 2014.1. But 2014.1 has runtime improvements for the tool which can be tested.
Regards,
Debraj
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Visitor
Visitor
5,729 Views
Registered: ‎06-13-2014

Hi debrajr,

 

Is there any update on the incremental compilation feature?

 

Regards,

Sc

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Observer
Observer
5,700 Views
Registered: ‎06-19-2014

I've just installed Vivado 2014.2 and this problem seems to be still present...when will the incremental compilation be available?

Thank you, Christophe

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Moderator
Moderator
5,696 Views
Registered: ‎04-17-2011

There is a lot of push for incremental compile even from our Sales folks and I would add your comments also to that. Currently it is not available but lets hope for that in the future release. If I get any info on the release date I would post here.
Regards,
Debraj
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Observer
Observer
5,297 Views
Registered: ‎09-30-2014

Has any progress been mode here? I recently started using Vivado 2014.2 and am experiencing these same exhaustive comilation times.

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Visitor
Visitor
5,022 Views
Registered: ‎11-21-2014

It seems this problem will remain unresolved for WinXP users since Vivado no longer supports this OS, starting from v2014.4. :( Too bad.

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Xilinx Employee
Xilinx Employee
4,988 Views
Registered: ‎10-24-2013

Hi,
For the Vivado 2014.4 release, Windows XP will no longer be supported. This is due, in large part, to Microsoft’s termination of Windows XP support.
Thanks,Vijay
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3,323 Views
Registered: ‎07-27-2015

Hi!

Just wondering if there are any news with that.
Im using 2015.1 and also expirenced these simulation log run due to reompiling...

 

Thank you

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Moderator
Moderator
3,305 Views
Registered: ‎04-17-2011

If there is no source code changes and no need to compile the code then you can skip compilation during re running simulation now with a TCL parameter:
set_property SKIP_COMPILATION 1 [get_filesets sim_1]
Regards,
Debraj
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3,298 Views
Registered: ‎07-27-2015

Does the simulator has an option to compile only the changes?
I mean if the change is very small and only in a small part in the design, does the tool compile all again?

thanks

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Xilinx Employee
Xilinx Employee
3,294 Views
Registered: ‎09-13-2014

You are looking for incremental compilation in Vivado Simulator, which is not yet supported so even if you do small change in design, it will compile the complete design.

 

But if your change is on test bench level related with some vector that you are driving, you can achieve the same functionality by TCLcommand  itself and in that case, you won't have to compile the design again.

 

--dhiRAj

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