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satguy
Explorer
Explorer
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Registered: ‎04-19-2018

A simple way to simulate (RTL) an IP block with AXI4 streams?

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I have some HLS functions packaged as IP, the use AXI stream for input and output. Now I would like to simulate in Vivado. The natural way that comes to my mind is building up a minimum system with a processor, DMA, memory... but that seems to me a lot. I know that eventually I will have to build that system, but for debugging purposes it will be good to check what is just created before going for more.

So, is it possible in vivado to have an RTL test bench feeding AXI4-stream data to an IP block?

UPDATE: I just found it's possible to have a BD with that IP block and have it VHDL-wrapped and synthesized, so the question becomes: How easy is to ceate a testbench sending AXI Stream values?

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richardhead
Scholar
Scholar
987 Views
Registered: ‎08-01-2012

I depends on your definition of "easy" and what the data in the interface is.

AXI4S is a very simple interface. You just need to assert tvalid alongside the data, and change the data when tready is high. This can easily be done in a looped process.

If you need more randomisation and data checking, you could roll your own verification IP, or try a BFM thats freely available, like here:

https://www.linkedin.com/pulse/axi4-stream-vhdl-verification-ip-now-available-free-uvvm-tallaksen/

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richardhead
Scholar
Scholar
988 Views
Registered: ‎08-01-2012

I depends on your definition of "easy" and what the data in the interface is.

AXI4S is a very simple interface. You just need to assert tvalid alongside the data, and change the data when tready is high. This can easily be done in a looped process.

If you need more randomisation and data checking, you could roll your own verification IP, or try a BFM thats freely available, like here:

https://www.linkedin.com/pulse/axi4-stream-vhdl-verification-ip-now-available-free-uvvm-tallaksen/

View solution in original post

satguy
Explorer
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Registered: ‎04-19-2018

Good to know, thanks.

I initially made a system with memory and DMA.... then I found an AXI stream FIFO can do the job with not that much hassle so I started that road.

But I keep the advice for the future.

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