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Adventurer
Adventurer
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Registered: ‎10-14-2017

ASIN function not decleared when using math_real library in Vivado 2018.3

Hi,

I'm trying to implement an ASIN function in hardware. The function should be able to handle various input data widths. For that I've chosen to use the LUT method where I generate appropriately sized ROMs which are initialized to correct data.

For initializing ROMs I've created a function which uses MATH_REAL package ASIN function. Syntax checker gives me an error that ASIN is not decleared, but I've read from other threads that this can be ignored as it's a bug. However when trying to simulate the deisgn it fails with the same reason:

 

ERROR: [VRFC 10-2989] 'asin' is not declared [C:/Users/User/Documents/Projektid/FPGA/Vivado/df_ver1/df_ver1.srcs/sources_1/new/arcsin_lut.vhd:77]
ERROR: [VRFC 10-3557] near 'integer' ; type conversion does not match type 'real' [C:/Users/User/Documents/Projektid/FPGA/Vivado/df_ver1/df_ver1.srcs/sources_1/new/arcsin_lut.vhd:78]
ERROR: [VRFC 10-1471] type error near tmp_value ; current type real; expected type std_ulogic_vector [C:/Users/User/Documents/Projektid/FPGA/Vivado/df_ver1/df_ver1.srcs/sources_1/new/arcsin_lut.vhd:79]

 

From other threads I read that it should be possible to use the math-real package in Vivado. So why am I getting this error? Can someone please point out what am I doing wrong?

My code is following:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.math_real.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity arcsin_lut is
    Port ( clk : in STD_LOGIC;
           s_axis_data : in STD_LOGIC_VECTOR (15 downto 0);
           s_axis_valid : in STD_LOGIC;
           s_axis_last : in STD_LOGIC;
           s_axis_ready : out STD_LOGIC;
           m_axis_data : out STD_LOGIC_VECTOR (15 downto 0);
           m_axis_valid : out STD_LOGIC;
           m_axis_last : out STD_LOGIC;
           m_axis_ready : in STD_LOGIC);
end arcsin_lut;

architecture Behavioral of arcsin_lut is
    
    -- type for creating ROM
    type mem_array is array (natural range 0 to 2**(s_axis_data'length-2)) of STD_LOGIC_VECTOR (s_axis_data'range);
	
    function createRomValues (elementCount : in natural) return mem_array is
	   variable argument   : real := 0.0;
	   variable tmp_value  : real := 0.0;
	   variable memory     : mem_array := (others => (others => '0'));
	begin
	   for i in 0 to (elementCount-1) loop  -- create as many elements as specified with function argument
	        tmp_value := ASIN(1.0-(real(i)*(2.0/real(elementCount-1)))); 
	        tmp_value := integer(round(tmp_value * real(elementCount)));
	        memory(i) := tmp_value;
	   end loop;   
	   return memory;
	end function CreateRomValues;
	
	constant ROM : mem_array := createRomValues(2**(s_axis_data'length-2)); 
begin end Behavioral;
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