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Adventurer
Adventurer
9,952 Views
Registered: ‎02-12-2015

AXI DMA - What's happening?!

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Hello,

 

I've been trying to get a counter's values to the PS from a custom axi peripheral. When I run my design from the sdk however, I never hit a break point in my interrupt. So I decided to check things were working as expected - I did this piece by piece up to the dma controller.

 

I got the expected data feed from my FIFO when I just held the ready signal high. But now, the dma sends this ready signal low after a few samples and it does not come back on...

 

I send M_AXI_S2MM_awready, M_AXI_S2MM_bvalid and M_AXI_S2MM_wready high after a short time (and hold high).  You can see from the attached waveform image that there is no data on the output of the dma.

 

Can I simulate the dma without a PS element in the block design? I'm not clear what the awcache output signifies?

blockDesign.png
waveform.png
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Adventurer
Adventurer
17,346 Views
Registered: ‎02-12-2015

Re: AXI DMA - What's happening?!

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solved by transferring the right amount of data out...!

View solution in original post

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Xilinx Employee
Xilinx Employee
9,941 Views
Registered: ‎08-02-2011

Re: AXI DMA - What's happening?!

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Hello,

 

Have you searched the forums at all? This is discussed quite a bit.

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Adventurer
Adventurer
9,930 Views
Registered: ‎02-12-2015

Re: AXI DMA - What's happening?!

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Unfortunatley I can't open the IP Example Design for the dma which I think from what I've read would help! I am struggling to find answers to the specific questions I asked in the documentation and in the forums.

 

Could you point me to any threads - my searching for axi dma, dma simulation etc hasn't answered why my dma seems to switch off after a few bytes.

 

Regards 

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Adventurer
Adventurer
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Registered: ‎02-12-2015

Re: AXI DMA - What's happening?!

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It seems the problem was with my AXI stream FIFO. It wasn't generating the last signal as I expected. I removed the fifo and connected my peripheral straight to the DMA and it seems to work.

 

The peripheral is a basic counter, that holds valid until the count hits a threshold, when the last is raised, then on the next cycle the valid is dropped and there is a delay before it all starts again.

 

It seems to work... I get interrupts and can validate the data in SDK when I am counting to 20 ish, and passing the count value as  32 bit data and transferring these. When I increase the count threshold - i.e there are more integers before the last signal is generated my software stalls in the interrupt handler - waiting for the idle bit in the S2MM_DMASR to be enabled. It seems that the DMA is always busy.

 

My question is, is there a data limit before the last signal should be triggered - and where is this defined? A DMA config option?

 

Thanks.

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Adventurer
Adventurer
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Registered: ‎02-12-2015

Re: AXI DMA - What's happening?!

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Just to add DMAIntErr bit is high when the program stalls (i.e sat waiting for the idle bit to be enabled)
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Adventurer
Adventurer
17,347 Views
Registered: ‎02-12-2015

Re: AXI DMA - What's happening?!

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solved by transferring the right amount of data out...!

View solution in original post

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Xilinx Employee
Xilinx Employee
9,838 Views
Registered: ‎08-02-2011

Re: AXI DMA - What's happening?!

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Hey Marc,

 

Sorry I missed this thread; but I'm glad you solved it.

 

Yeah, tlast must be asserted on or before the number of bytes configured in the length register.

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