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Voyager
Voyager
123 Views
Registered: ‎01-28-2008

AXI IP Module not found in simulation - Testcase

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Hi folks,

  I've updated to 2018.2.2 last week and a new issue has popped up during behavioral simulation. The full design builds to a bitfile without any issues.

  In a nutshell, any AXI IP fails to compile during simulation with a similar message:

ERROR: [VRFC 10-2063] Module <axi_clock_converter_v2_1_16_axi_clock_converter> not found while processing module instance <inst> [/home/pcarr/Work/Pivotal/test-build/vivado/test_axi_ip/test_axi_ip.ip_user_files/bd/axi_ic/ip/axi_ic_auto_cc_0/sim/axi_ic_auto_cc_0.v:194]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.

  I have included a small testcase with a simple AXI interconnect that shows the error message every time. Sourcing the test_axi_ip.tcl recreates the project with a BD including the interconnect. Attempting to run a behavioral simulation shows the message above.

  The .zip file includes the test_axi_ip.tcl and the axi_ic.tcl scripts. To run, in Tcl shell please enter:

  > source test_axi_ip.tcl

Any pointers will be greatly appreciated.

Thanks,

-Pat

 

https://tuxengineering.com
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1 Solution

Accepted Solutions
Voyager
Voyager
64 Views
Registered: ‎01-28-2008

Re: AXI IP Module not found in simulation - Testcase

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The issue is known in 2018.2.2 and may be workaround by disabling the use of precompiled IP libraries.

The Tcl command that worked around it is:

set_property sim.use_ip_compiled_libs 0 [current_project]

Credit to @paulleons: https://forums.xilinx.com/t5/Simulation-and-Verification/Vivado-example-design-simulation-error/m-p/915050/highlight/true#M24323

 

Thanks,

-Pat

 

https://tuxengineering.com
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4 Replies
Voyager
Voyager
82 Views
Registered: ‎01-28-2008

Re: AXI IP Module not found in simulation - Testcase

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Folks,

  I can confirm this issue happens on 2018.2.2, but doesn't happen in 2018.2 or 2018.2.1.

  There's another user with the same duplicate issue: https://forums.xilinx.com/t5/Simulation-and-Verification/ERROR-VRFC-1-2063-Module-not-found-with-Vivado-2018-2-2/td-p/918041

Thanks,

-Pat

 

https://tuxengineering.com
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Voyager
Voyager
68 Views
Registered: ‎01-28-2008

Re: AXI IP Module not found in simulation - Testcase

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@graces

  I see that you mentioned a known simulation bug in 2018.2.2 regarding pre-compiled IP missing in installation directory.

  Can the issue on this thread be related to that known bug?

Thanks,

-Pat

 

https://tuxengineering.com
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Voyager
Voyager
65 Views
Registered: ‎01-28-2008

Re: AXI IP Module not found in simulation - Testcase

Jump to solution

The issue is known in 2018.2.2 and may be workaround by disabling the use of precompiled IP libraries.

The Tcl command that worked around it is:

set_property sim.use_ip_compiled_libs 0 [current_project]

Credit to @paulleons: https://forums.xilinx.com/t5/Simulation-and-Verification/Vivado-example-design-simulation-error/m-p/915050/highlight/true#M24323

 

Thanks,

-Pat

 

https://tuxengineering.com
0 Kudos
Xilinx Employee
Xilinx Employee
48 Views
Registered: ‎07-16-2008

Re: AXI IP Module not found in simulation - Testcase

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Yes, that should be the cause.

Compiling the IP static files at run time is one workaround.

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