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Explorer
Explorer
583 Views
Registered: ‎01-15-2019

AXI Interconnect in Block Design -> how to simulate?

Hi All,

I have a Vivado Project, which consists of a Block Design and RTL files. 

The Block Design consists of Zynq and AXI Interconnect. 

I want to simulate the RTL along with AXI Interconnect ... How can I do so? The AXI Interconnect is a part of the Block Design... Is there a way to create an HDL wrapper for IP, which is a part of Block Design?  

Thank you!

 

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Xilinx Employee
Xilinx Employee
461 Views
Registered: ‎10-30-2017

Re: AXI Interconnect in Block Design -> how to simulate?

Hi @ldm.eth ,

Create the HDL wrapper for the block design and then the AXI inter connect signals will come show in RTL. to Create HDL wrapper right click on BD and click create HDL wrapper.

Best Regards,
Srikanth
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Explorer
Explorer
440 Views
Registered: ‎01-15-2019

Re: AXI Interconnect in Block Design -> how to simulate?

 

OK, but my Block Design includes both the Zynq & AXI Interconnect where Zynq drives the AXI Interconnect input ports... So, if I'll create an HDL Wrapper, it will only has the Zynq's ports and output ports of AXI Interconnect (no input ports of AXI Interconnect will be present in the HDL Wrapper).

So, what's the solution? How to simulate my design by driving the AXI Interconnect ports (I'd like the AXI Interconnect ports will be driven by TestBench and not by Zynq)?

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Moderator
Moderator
413 Views
Registered: ‎04-24-2013

Re: AXI Interconnect in Block Design -> how to simulate?

Hi @ldm.eth ,

I'm not clear on your use case here

If you want to simulate an AXI Interconnect that isn't driven by the Zynq, then why not copy and paste the one you have into a new Block Design and create a wrapper on that?

You can get access to the internal signals. If you open the Simulation Sources and drill down below the block design you will see the RTL for the design.

Capture2.PNGCapture1.PNG

You could then wrap this in a test bench

Best Regards
Aidan

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