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Visitor
Visitor
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Registered: ‎05-07-2018

AXI VIP clock cycles from AWVALID to AWREADY handshake.

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I'm using AXI Verification IP v1.1 from Vivado Design Suite.

I need the clock cycles from AWVALID to AWREADY handshake.

I likewise need the clock cycles from ARVALID to ARREADY handshake.

 

If READY is already high when VALID gets asserted, then the count can be ZERO.

 

I'm using axi_monitor_transaction class from *.monitor.item_collected_port.get(coverage_transaction);.

 

So far, addr_phase_end works as expected, but addr_phase_start does not work and addr_accepted_cycles also does not work.

 

I'm using slaves with and without memory.

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Visitor
Visitor
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Registered: ‎05-07-2018

For the attached waveform, I get this:

 

addr_phase_end 2230000, addr_phase_start 210000

addr_valid_assert_time 2230000, addr_ready_assert_time 210000

addr_accepted_cycles -202

 

So, the VIP thinks the address phase starts when ready is asserted.   This does not make sense, as the AXI slave can pulse READY without VALID and there is no address transfer, so nothing is started.

 

In any case, I can get the info I need by using  addr_valid_assert_time - addr_phase_end.

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awvalid_awready.bmp
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Moderator
Moderator
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Registered: ‎04-24-2013

Hi @giantpeach,

 

Have you looked at the example designs?

 

The easiest way to generate these is to create a block diagram, add the Axi VIP and right click it.

Then choose Open IP Example design.

 

This provides a range of different configuration examples that you can run.

As the AXI VIP is written in SystemVerilog, make sure that the target Language is set to Verilog in the project settings.

 

Best Regards
Aidan

 

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Highlighted
Visitor
Visitor
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Registered: ‎05-07-2018

For the attached waveform, I get this:

 

addr_phase_end 2230000, addr_phase_start 210000

addr_valid_assert_time 2230000, addr_ready_assert_time 210000

addr_accepted_cycles -202

 

So, the VIP thinks the address phase starts when ready is asserted.   This does not make sense, as the AXI slave can pulse READY without VALID and there is no address transfer, so nothing is started.

 

In any case, I can get the info I need by using  addr_valid_assert_time - addr_phase_end.

View solution in original post

awvalid_awready.bmp
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