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morlior.deep
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Registered: ‎07-18-2019

AXI_VIP integration in Vivado 2020.1 project - As a master, in order to connect it to my DUT slave

Hi all.

I want to integrate the AXI_VIP unit as a master, and connect it to my DUT slave.
 
I'm using Vivado in batch mode, when running a simulation. I'm not using the gui to compile\elaborate, but just to run the simulation when Vivado Simulator turns on (xelab, then xsim, by command line cmds).
 
Trying to integrate the AXI_VIP unit into my project, I see that:
 
1. The AXI VIP isn't being "found" as an ip in use, when the Vivado Simulator is being opened.
To have the IP found in "get_ips" tcl command, I have to send these two tcl commands:
  • read_ip  /home/vivado_workspace/axi_vip_0_13APR21/axi_vip_0_13APR21.xci
  • catch { config_ip_cache -export [get_ips -all axi_vip_0_13APR21] }
    <result>: 0
Then when sending "get_ips" tcl command, 
<result>: axi_vip_0_13APR21
 

2. I see that the IF (interface) seems to be not recognised in the compiled project.


In comparison to the example project of the AXI_VIP, where there is
DUT > ex_design > axi_vip_mst > inst > IF > PC &CB:
 

[See attached ex_design_IF_shown.png.]

 
When I compile my project, no IF and below are shown, under my tb:
 

[See attached user_tb_no_IF_shown.png.]

 
3. In order to run and use the AXI VIP properly, I also need to see the notice of
"XilinxAXIVIP: Found at Path: axi_vip_0_13APR21_exdes_adv_mst_active__pt_passive__slv_comb.DUT.ex_design.axi_vip_mst.inst" by the Vivado Simulator. 
As described in PG267 pg267-axi-vip.pdf , p.47:
 

[See attached pg267_p47.png.]

Currently I don't see it.. 
 
4. Is it needed to add the axi_vip_0_13APR21/axi_vip_0_13APR21_sim_netlist.v (that has been 
produced before by the AXI_VIP generation (In IP catalog)) to the .f of the project\elaboration\xsim run?
 
When I have this file in the .f file of the Vivado xelab\xsim, the situation of the simulator is as was described above.
When I don't call also to the axi_vip_0_13APR21/axi_vip_0_13APR21_sim_netlist.v in the .f file, the compilation\elaboration fails with this error:
"
In file included from xsim.dir/work.user_tb/obj/sysc_interface.cc:2:0:
./xsim.dir/work.user_tb/obj/sysc_interface.h:1:31: fatal error: axi_vip_0_13APR21.h: No such file or directory
 #include "axi_vip_0_13APR21.h"
                               ^
compilation terminated.
gcc: error: xsim.dir/work.user_tb/sysc_interface.so: No such file or directory
ERROR: [XSIM 43-3238] Failed to link the design.
"
 
I've already added "-i  <GITROOT>/axi_vip/axi_vip_0_13APR21/sim/ " to the compilation cmd.
 
 
What should I do to get this work? What am I missing?
 
Thank you so much in advance,
 
I'll appreciate it very much.
 
Thanks
 
 
pg267_p47.png
ex_design_IF_shown.png
user_tb_no_IF_shown.png
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2 Replies
bandi
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Moderator
295 Views
Registered: ‎09-15-2016

Hi @lior,

Can you please share the test case to check this issue at our end with the exact steps and scripts you have followed to compile the files in batch mode.

Thanks & Regards,
Sravanthi B
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morlior.deep
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Registered: ‎07-18-2019

Hi @bandi,

Thanks for your reply.

 

Meanwhile I've found that the needed file for compilation is axi_vip_0_/axi_vip_0_sim_netlist.v that has been produced in the IP generation.

But, It isn't mentioned in the needed_files list, also when typing tcl cmd "get_files -compile_order sources -used_in simulation -of_objects [get_files <axi_vip_0>.xci]" in the tcl console of Vivado Simulator.

 

What are the needed IP files to be compiled in the project for running a simulation? As mentioned also in my origin question, without this "axi_vip_0_sim_netlist.v" in the compiled files - The compilation for simulation has been failed..?

 

Another question please: 

In order to re-generate an ip for a batch-mode vivado simulation run, can I export the IP with its settings\parameter to a tcl file, without all the project?

I want to include in my flow a generation of an IP (in the out-of-context mode) then run a simulation with them (batch-mode xsim) within all my other source files.

Is there a way that doesn't include a complete project export to a tcl or a write_bd tcl (I don't have any BD in my design)?

Thanks!

 

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