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Visitor ctstone
Visitor
202 Views
Registered: ‎06-11-2017

AXI VIP read_data mismatch

Hi all,

Recently, I am working on AXI VIP as slave with memory, the reference tutorial is this: 

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841614/Validating+a+master+AXI4+interface+using+the+Verification+IP+as+a+slave#ValidatingamasterAXI4interfaceusingtheVerificationIPasaslave-Project

My custom IP has 128-bit AXI data channel, which is different from the tutorial above.

After Step 5 : Launch the simulation, I assumed the AXI VIP will output the same read_data as write_data.

However, it seems that only LSB 32-bit is the same.

I was wondering whether can I trace the AXI VIP RTL code.

Because in the simulation scope, the "Go to Source Code" is not available.

Both vivado 2017.2/2018.2 and AXI VIP v1.0.2/v1.1 are tried and both versions show the same result.

 

Thanks for your help!

 

AXI_VIP_rdata_mismatch.PNG
go_to_source_code.PNG
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1 Reply
Xilinx Employee
Xilinx Employee
111 Views
Registered: ‎10-04-2016

Re: AXI VIP read_data mismatch

Hi @ctstone,

Could you post the complete waveforms for your custom master's AXI Read command? Could you also post the output from the AXI VIP when it detects this read access? 

If I had to guess, one of two things is happening:

1. The data width of the AXI VIP is not set correctly. Please check the configuration GUI and make sure it has a 128 bit interface.

2. The ARSIZE field in your master's read command is not correct. For a 128-bit read, this should be set to 3'b100.

The AXI VIP code is available, but I'm not sure how to make it trace-able with XSIM. You can see the source under <Vivado install directory>\data\xilinx_vip.

Regards,

Deanna

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