I have question about AXI arvalid signal used for interfacing with DDR axi controller in Zynq.
if I do not remove i_axi_arready , I will have deadlock issue.
If I remove i_axi_arready , I will have issue arising from DDR periodic mechanism such as auto-refresh.
What could I do ?
Someone told me the following which I do not understand:
VALID signal needs to be set (initially) independent of READY signal, and then only ever adjusted if !(VALID && !READY)
always @(posedge clk)
begin
if(reset) o_axi_arvalid <= 0;
// AXI specification: A3.3.1 Dependencies between channel handshake signal
// the VALID signal of the AXI interface sending information must not be dependent on
// the READY signal of the AXI interface receiving that information
// this is to prevent deadlock
// since AXI slave could waits for i_axi_arvalid to be true before setting o_axi_arready true.
// Note: VALID cannot be dependent upon READY, but READY can be dependent upon VALID
// VALID signal needs to be set (initially) independent of READY signal,
// and then only ever adjusted if !(VALID && !READY)
else o_axi_arvalid <= /*i_axi_arready &&*/ (!cache_is_full);
end
