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rayhaynes
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Registered: ‎02-08-2013

AXI simulation as supplied by Xilinx won't work

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I have followed step by step this video how-to-use-axi-verification-ip-to-verify-debug-design-using-simulation using 2017.1 and get an error. The error messages point to the elaborate.log file shown below. As I said I followed the video exactly. What could my issue be?

 

Vivado Simulator 2017.1
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2017.1/bin/unwrapped/win64.o/xelab.exe -wto 0ed9b9376cb448a1a6146da580a0ac48 --debug typical --relax --mt 2 -L axi_infrastructure_v1_1_0 -L xil_common_vip_v1_0_0 -L smartconnect_v1_0 -L axi_protocol_checker_v1_1_13 -L axi_vip_v1_0_1 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot axi_vip_0_exdes_adv_mst_active__pt_passive__slv_comb_behav xil_defaultlib.axi_vip_0_exdes_adv_mst_active__pt_passive__slv_comb xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
ERROR: [VRFC 10-900] incompatible complex type assignment [../../../imports/axi_vip_0_mst_stimulus.sv:46]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.

Regards, Ray Haynes, Ostendo Technologies, Inc. Carlsbad, CA
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graces
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Registered: ‎07-16-2008

In the example design, did you set the target language to VHDL? If so, change to Verilog and re-generate the output products. Then re-launch simulation and see if the error is gone.

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rayhaynes
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Registered: ‎02-08-2013

Update- If I run 2017.2 on a local drive I can get the simulation to run which I'm hoping will point to the way to get my simulation environment up and running.

 

Sometimes I start to wonder I can't follow directions but then this happens and it turns out it's all Vivado bugs baby!!!!!!!!!!!!!!

Regards, Ray Haynes, Ostendo Technologies, Inc. Carlsbad, CA
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graces
Moderator
Moderator
4,920 Views
Registered: ‎07-16-2008

In the example design, did you set the target language to VHDL? If so, change to Verilog and re-generate the output products. Then re-launch simulation and see if the error is gone.

-----------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs.
-----------------------------------------------------------------------------------------------------------------------

View solution in original post

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rayhaynes
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Registered: ‎02-08-2013

Ok that seems to be one of the issues. The new instance of Vivado opened when "Open IP Example Design.." inherits the VHDL setting from the original project setting even though this IP can't really be simulated using VHDL. I think when the launcher which launching the new instance of Vivado and generating the outputs it should have prompted me to change the language. Maybe in 2017.3. 

 

95% of our designs are in VHDL with using verilog only when there is not a VHDL option. I will remember to try the verilog language if I run into other problems.

 

The path problem still remains where I get the can't generate simulation database error unless the project is in a root folder on C:. Won't work on UNC paths/Mapped UNC Paths/or in a folder on my desktop. This is not show stopper.

 

Thanks for your language change suggestion. 

Regards, Ray Haynes, Ostendo Technologies, Inc. Carlsbad, CA
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