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scmicron
Participant
Participant
1,493 Views
Registered: ‎08-23-2017

Abnormal program termination (11) during simulation

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Dear all,

 

it happens quite often, the following message appears while doing simulation of VHDL design usign Vivado 2017.2:

 

****** xsim v2017.2 (64-bit)
**** SW Build xxxxxxx on Thu Jun 15 18:39:10 MDT 2017
**** IP Build yyyyyyy on Thu Jun 15 19:58:00 MDT 2017
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

start_gui
Abnormal program termination (11)
Please check 'hs_err_pid32752.log' for details

 

and the contents of the log file are:

 

#
# An unexpected error has occurred (11)
#
Stack:
/apps/xilinx/2017.2/Vivado/2017.2/tps/lnx64/jre/lib/amd64/server/libjvm.so(+0x923da9) [0x7f483d75fda9]
/apps/xilinx/2017.2/Vivado/2017.2/tps/lnx64/jre/lib/amd64/server/libjvm.so(JVM_handle_linux_signal+0xb6) [0x7f483d7663f6]
/apps/xilinx/2017.2/Vivado/2017.2/tps/lnx64/jre/lib/amd64/server/libjvm.so(+0x9209d3) [0x7f483d75c9d3]
/lib64/libpthread.so.0() [0x3bb760f7e0]
/apps/xilinx/2017.2/Vivado/2017.2/lib/lnx64.o/librdi_simbridge_kernel.so(SimBridge::WdbCommonReader::getValueEvent(long long, std::vector<SimBridge::WdbScalarBTree*, std::allocator<SimBridge::WdbScalarBTree*> > const&, SimBridge::WdbTimeByteValues&) const+0x7e) [0x7f4844b9af8e]
/apps/xilinx/2017.2/Vivado/2017.2/lib/lnx64.o/librdi_simbridge_kernel.so(SimBridge::WdbLiveReader::getValueEvent(long long, std::vector<SimBridge::WdbScalarBTree*, std::allocator<SimBridge::WdbScalarBTree*> > const&, SimBridge::WdbTimeByteValues&) const+0x38) [0x7f4844bac628]
/apps/xilinx/2017.2/Vivado/2017.2/lib/lnx64.o/librdi_wavedata.so(SimBridge::WdbDataSource::getValueTime(SimBridge::DataObj const*, long long, long long&, SimBridge::Value&) const+0x177) [0x7f4865e46107]
/apps/xilinx/2017.2/Vivado/2017.2/lib/lnx64.o/librdi_wavedata.so(SimBridge::WdbDataSource::getValue(SimBridge::DataObj const*, long long, SimBridge::Value&) const+0x1a) [0x7f4865e4662a]
/apps/xilinx/2017.2/Vivado/2017.2/lib/lnx64.o/librdi_wavedata.so(SimBridge::DataObjMgr::getValue(SimBridge::DataObj const*, long long, SimBridge::ValueFormat const&, bool, SimBridge::Value&) const+0x383) [0x7f4865e429e3]
/apps/xilinx/2017.2/Vivado/2017.2/lib/lnx64.o/librdi_wavedata.so(SimBridge::DataReader::getValue(SimBridge::IDataObj const*, long long, SimBridge::ValueFormat const&, SimBridge::Value&) const+0xdd) [0x7f4865e4cb0d]
/apps/xilinx/2017.2/Vivado/2017.2/lib/lnx64.o/librdi_wavedata.so(SG_Model::Model::getValue(SG_Model::WVDataObject const*, long long, SimBridge::Radix const&) const+0x101) [0x7f4865e91d81]
/apps/xilinx/2017.2/Vivado/2017.2/lib/lnx64.o/librdi_wavedata.so(WaveViewer::WVWaveformModel::getWaveformTooltip[abi:cxx11](SG_Model::WVDataObject const*, long long)+0x283) [0x7f4865f17733]
/apps/xilinx/2017.2/Vivado/2017.2/lib/lnx64.o/librdi_wavedata.so(WaveViewer::WVWaveformPanel::getWaveformTooltip[abi:cxx11]()+0xd4) [0x7f4865f1d984]
/apps/xilinx/2017.2/Vivado/2017.2/lib/lnx64.o/librdi_wavedata.so(WVExecutive::getTooltipTextDelayed[abi:cxx11]() const+0x77) [0x7f4865eed667]
/apps/xilinx/2017.2/Vivado/2017.2/lib/lnx64.o/librdi_wavedata.so(Java_ui_views_waveform_waveformi_WVExecutive_1getTooltipTextDelayed+0x40) [0x7f4865f3eb10]
[0x7f482eaad031]

 

Any idea of how to fix this?

 

Thanks

Cheers

 

S

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1 Solution

Accepted Solutions
syedz
Moderator
Moderator
2,134 Views
Registered: ‎01-16-2013

@scmicron,

 

RHEL 4.4 is unsupported OS with Vivado 2017.2. Please use the supported OS and check if the issue resolves. 

https://www.xilinx.com/support/answers/54242.html

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------

View solution in original post

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4 Replies
shameera
Moderator
Moderator
1,487 Views
Registered: ‎05-31-2017

Hi @scmicron,

 

Can you please provide a test case which would help the community to debug further.

And also Can you please specify the OS which you are using.

 

Thanks & Regards,
A.Shameer.

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scmicron
Participant
Participant
1,475 Views
Registered: ‎08-23-2017

Hello @shameera,

 

I cannot provide the test case to the public. What I can say is that the design contains VHDL, Verilog and SystemVerilog sources and the test-bench is written in Tcl. We are running over Red Hat 4.4.7-18, kernel version 2.6.32-696.3.2.el6.x86_64.

 

Cheers

S

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syedz
Moderator
Moderator
2,135 Views
Registered: ‎01-16-2013

@scmicron,

 

RHEL 4.4 is unsupported OS with Vivado 2017.2. Please use the supported OS and check if the issue resolves. 

https://www.xilinx.com/support/answers/54242.html

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------

View solution in original post

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shameera
Moderator
Moderator
1,467 Views
Registered: ‎05-31-2017

Hi @scmicron,

 

As, @syedz pointed out RHEL 4.4 is not supported with Vivado 2017.2 because of this you might be facing this issue. So, please use the supported OS as suggested in page 8 of UG973 to use Vivado 2017.2 without any issues.

 

Thanks & Regards,
A.Shameer.

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