04-11-2019 02:00 AM
I have an Error message see attachment when run Simulation .
I'm using : Vivado 2017.4 with the license for ZCU102, Windows 10 PRO.
Synthesis and Implementation is done successfully.
I can't explain why have the Simulator error message related to the standard IOBUF primitive and the rest
VRFC 10-2063 related errors. Can you advise?
04-11-2019 02:17 AM
Are you using the Xilinx unisim library component?
04-11-2019 02:51 AM
About Unisim library Xilinx wrote for Verilog : " When you invoke the simulator from within Project Navigator, the simulator script automatically references the UNISIMS_VER library" and it also doesn't explain the situation with my own M24C00 behav module.
04-14-2019 06:05 PM
For Vivado Simulator, Xilinx libraries are pre-compiled and should be correctly referenced in simulaiton.
From the error messages, it looks not only IOBUF, but also some user modules are not found. Have you generated the block design successfully?
04-15-2019 01:45 AM
See please attachment I think it indicates the block design generated correctly. Indeed the Simulator message about module instance <top_bd_i> looks strange.
I'm using the Vivado built-in Simulator and what arguments in COMPILE_SIMLIB ( Vivado 2017.4) command should I use to be sure all Xilinx libraries compiled correctly as you wrote?
One more question in case if I'll use in the testbench tb_top.sv the the conditional directive IFDEF TYPE_A for example, how can I start the simulation from TCL Console and Select TYPE_A option for IFDEF directive?