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766 Views
Registered: ‎02-26-2019

Accesing an internal signal of VHDL module from a Verilog testbench

Hi,

How can i force an internal signal in VHDL modules from a Verilog testbench?

Can i do this with Vivado Simulator?

I tried this verilog code for this purpose:

initial
begin

#5000

force board.DUT.PCIE_IP_CFG.pipe_mmcm_reset_n = 1'b1;

#100

release board.DUT.PCIE_IP_CFG.pipe_mmcm_reset_n;

end

 

and i got this error:

ERROR: [XSIM 43-3138] "..../top_level/sim/board.v" Line 253. Cross Language Hierarchical name(board.DUT.PCIE_IP_CFG.pipe_mmcm_reset_n) is not supported in this context.

 

Thanks.

Mustafa

mustafasu
0 Kudos
2 Replies
graces
Moderator
Moderator
741 Views
Registered: ‎07-16-2008

The feature is on roadmap.

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Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs.
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0 Kudos
718 Views
Registered: ‎02-26-2019

Is it possible with other simulators such as Modelsim?

Mustafa.

mustafasu
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