03-26-2019 03:37 PM
How can i force an internal signal in VHDL modules from a Verilog testbench?
Can i do this with Vivado Simulator?
I tried this verilog code for this purpose:
force board.DUT.PCIE_IP_CFG.pipe_mmcm_reset_n = 1'b1;
and i got this error:
ERROR: [XSIM 43-3138] "..../top_level/sim/board.v" Line 253. Cross Language Hierarchical name(board.DUT.PCIE_IP_CFG.pipe_mmcm_reset_n) is not supported in this context.
03-26-2019 06:30 PM
The feature is on roadmap.