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Visitor
Visitor
1,441 Views
Registered: ‎04-29-2019

Add support for VUnit

In my new project I use a CI pipleline for automated testing and it makes things much easier. Sigasi already integrated VUnit into Sigasi Studio.

XSIM should support at least all the VHDL features needed for VUnit.

Atm this is not possible with Vivado/Xsim and makes it useless to me.

It is very poor that I have to rely on third party tools to work with the design flow that is state of the art

7 Replies
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1,336 Views
Registered: ‎04-09-2020

I have the same problem in my company. I can't use Xilinx IPs with VUnit+xsim.

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Visitor
Visitor
1,317 Views
Registered: ‎06-01-2019

I agree, same issue at my job, we use Vunit and it would be a great addition.

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Observer
Observer
1,027 Views
Registered: ‎07-02-2018

I am also interested in using Vunit with Vivado simulator. I would not like to have to buy a expensive simulator when I have the Vivado tool.

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Scholar
Scholar
1,020 Views
Registered: ‎08-01-2012

@sasn1no expensive simulator needed.  GHDL supports vunit and is free and open source.

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Visitor
Visitor
1,008 Views
Registered: ‎04-29-2019

@richardheadunfortunately GHDL supports only simulation of VHDL code. Many (all?) Xilinx IP cores have Verilog simulation models.

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Observer
Observer
1,007 Views
Registered: ‎07-02-2018

@richardhead The main problem is GHDL just support vhdl, in my case I need to use Vunit with Verilog. I´ve been cheking the possibility to simulate with other open source simulators but it is not possible, only with Mentor...

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Scholar
Scholar
994 Views
Registered: ‎08-01-2012

@hofo 

What cores are you trying to use?

Ram can easily be infered from VHDL, so a generic FIFO can also be easily written in VHDL.

if anything else, then yes, its a pain, and mixed language is the only option.

 

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