04-21-2020 01:48 AM
In my new project I use a CI pipleline for automated testing and it makes things much easier. Sigasi already integrated VUnit into Sigasi Studio.
XSIM should support at least all the VHDL features needed for VUnit.
Atm this is not possible with Vivado/Xsim and makes it useless to me.
It is very poor that I have to rely on third party tools to work with the design flow that is state of the art
04-26-2020 11:00 PM
I am also interested in using Vunit with Vivado simulator. I would not like to have to buy a expensive simulator when I have the Vivado tool.
04-27-2020 12:52 AM - edited 04-27-2020 12:56 AM
04-27-2020 12:55 AM - edited 04-27-2020 12:57 AM
@richardhead The main problem is GHDL just support vhdl, in my case I need to use Vunit with Verilog. I´ve been cheking the possibility to simulate with other open source simulators but it is not possible, only with Mentor...
04-27-2020 01:05 AM
What cores are you trying to use?
Ram can easily be infered from VHDL, so a generic FIFO can also be easily written in VHDL.
if anything else, then yes, its a pain, and mixed language is the only option.
02-04-2021 05:29 AM - edited 02-04-2021 05:29 AM
Support for VUnit with Vivado would be a big plus to me as well. Unfortunately, at the moment I cannot see any sign that this will happen any time soon.
At a minimum, it would be nice if Vivado could analyze testbenches, which include the VUnit context clause, without throwing an error.
07-02-2021 05:26 AM
When can we have proper VHDL2008 support within xsim such that xsim becomes a "recommended simulator" for VUnit?
Proper VHDL2008 support for xsim is being asked by developers for over 5 yrs and Xilinx has done little for this cause till date.
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer has solved your problem
Asking for solutions to problems via PM will be ignored.
07-16-2021 09:53 AM
We also require this. As it stands the Xilinx simulator is simply not useful as a verification tool. Xilinx reps, please reach out to anyone in this thread or in the Vunit issues here https://github.com/VUnit/vunit/issues. I am sure all would be happy to help determine the minimum necessary changes for the simulator to at least function with Vunit. I am not an expert but will devote time to the issue if Xilinx will work with us.
It is in Xilinx's best interest to make the simulator functional as this keeps small design teams inside your environment. By forcing users to turn to 3rd party tools we now consider how to become vendor agnostic, and therefore less stuck in Xilinx world if a better deal becomes available with other vendors. For many of us the simulator performance is not great but sufficient, we just need the ability to use this already existing CI tool.
Riviera already has official support for VHDL 2019 while the Xilinx simulator still can't support 2008, yet the synthesizer has for years.