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_risc_
Visitor
Visitor
441 Views
Registered: ‎03-24-2021

Advance Verification possible with Vivado?

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I come from a larger company background where we used synopsys tools like vcs to run advance verification with systemverilog and batch-mode test cases on the command line. Is this type of verification possible at all with Vivado? 

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kdeshwal
Xilinx Employee
Xilinx Employee
335 Views
Registered: ‎11-12-2019

Hi @_risc_ ,

Vivado Simulator is a hardware description language (HDL) event-driven simulator that supports behavioral and timing simulation for single language and mixed language designs.

Feature highlights:

  • SystemVerilog (Including constraint randomization and functional coverage)
  • Verilog 2001
  • VHDL 93 and VHDL 2008
  • UVM 1.2
  • Standard Delay Format (SDF) 3.0 for timing simulation
  • Switching Activity Interchange Format (SAIF) for power analysis
  • Value Change Dump (VCD) support

Please check out the link for more details - https://www.xilinx.com/products/design-tools/vivado/simulator.html#standards 

Thanks,
Kuldeep 

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richardhead
Scholar
Scholar
427 Views
Registered: ‎08-01-2012

I think the answer is yes and no

Xsim can be scripted and batch driven, and does support UVM, but I think the features may be quite a way behind VCS.

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kdeshwal
Xilinx Employee
Xilinx Employee
336 Views
Registered: ‎11-12-2019

Hi @_risc_ ,

Vivado Simulator is a hardware description language (HDL) event-driven simulator that supports behavioral and timing simulation for single language and mixed language designs.

Feature highlights:

  • SystemVerilog (Including constraint randomization and functional coverage)
  • Verilog 2001
  • VHDL 93 and VHDL 2008
  • UVM 1.2
  • Standard Delay Format (SDF) 3.0 for timing simulation
  • Switching Activity Interchange Format (SAIF) for power analysis
  • Value Change Dump (VCD) support

Please check out the link for more details - https://www.xilinx.com/products/design-tools/vivado/simulator.html#standards 

Thanks,
Kuldeep 

-------------------------------------------------------------------------------------------------------------
Please give Kudo and Accept as a Solution if solution provided seems helpful.
Have a look at our Versal Design Process Hub, Versal Blogs and the Versal Forum Useful Resources
-------------------------------------------------------------------------------------------------------------

View solution in original post