I would like to know if anyone is using UVVM and Vivado xsim as the simulator.
In Summer 2018 I going through the bitvis webpage, https://bitvis.no/dev-tools/uvvm/ , I was disappointed when I saw the list of "Supported simulators" (just scroll down to the end of link posted).
For Vivado the status then and now is "Vivado: Awaiting proper VHDL 2008 support".
It is now 2021 and I want to know if things have improved with xsim.
So if someone is using UVVM and xsim please share your experiences.
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UVVM has extensive use of package generics, generic types, generic functions. Basically all the VHDL 2008 items that the synthesis, but not simulator, supports.
It also needs support for unconstrained array and record types. Again, a lacking simulator feature.
Fingers crossed for support in 2021.1. But Im not holding my breath.
Otherwise it works with GHDL (which is free)