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fbartra
Visitor
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Registered: ‎10-27-2010

Array signal updated by different procedures gives undifined simulation output value

I am using wedpack ISE, spartan 3

 

I have declared an array signal in my code as follows:

 

  • type Array256x8  is array (0 to 255)  of std_logic_vector(7 downto 0);
  • signal FpgaReg : Array256x8 := ((others => (others => '0')));

When simulating my code:

 

  • if at least one pointer to a address is a signal (not a fixed value, i.e. X"03" instead of my_value) then I get a "x" and "red colored waveform" when simulating this code
  • otherwise, if the pointer to all addresses are a fixed value then I get the right value when simulating this code

couldn't each address of this array be writen (modified) by different procedures?

 

There are no erros or warning when I compile my code

 

any suggestions?

 

Thank you

 

Fausto bartra

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5 Replies
jmcclusk
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Registered: ‎02-24-2014

Try switching your memory declaration from a signal to a shared variable.   That should get rid of the conflicts in simulation.

Don't forget to close a thread when possible by accepting a post as a solution.
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richardhead
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Registered: ‎08-01-2012

 Please post the code, it is difficult to tell whats going on without a reference.

 

Points to note: In VHDL, each element of an array IS a separate object, so each element can be written from a separate process, unless there is a loop involved somewhere. BUT, this will NOT infer a RAM.

 

@jmcclusk A shared variable is only likely to mask the problem if there are multiple drivers in the code, and create race conditions during simulation. A shared variable should only be used if you are trying to infer write-first ram. Otherwise I highly recommend you use a signal, exactly for the reasons the OP is having problems with.

fbartra
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Registered: ‎10-27-2010

Voyager:

 

thank you it works

Just one problem, ISIM does not support variable tracing

 

thanks

 

Fausto Bartra

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fbartra
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Registered: ‎10-27-2010

Richard:

 

here is my code: I have trimmed as much as I could to show where the problem is

two processes access the same array FpgaReg but different locations

Thank you in advance

 

type Array256x8  is array (0 to 255)  of std_logic_vector(7 downto 0);

signal FpgaReg : Array256x8 := ((others => (others => '0')));

 

 

----------------------------------------
--            MCU Interface
----------------------------------------
McuInterface: process(CLK)
begin
    if falling_edge(CLK) then
        if (bufMCU_CSn = '1') then        -- When CSn is HIGH, state machine gets reset
           
            FpgaReg(CONV_INTEGER(ADDR_FPGA_VERSION_HIGH)) <= VER_HIGH;
          
            ---------------------------------------------------------------

        else    -- CSn is LOW
            case McuState is   

                when FpgaWrite =>
                                FpgaReg(CONV_INTEGER(FpgaAddress)) <= bufMCU_D_IN; <-- if FpgaAddress changed with a value, no problems

...

    end if;
end process McuInterface;   

 

------------------------------------

KpDebounce: process(CLK)
begin
    if rising_edge(CLK) then
        if P10ms = '1' then
        
            case KeypadDebState is
            
      
                
                when FoundKey =>                
                    -- flag MCU
                    FpgaReg(CONV_INTEGER(KP_LED))(3 downto 0) <= LastKB; <-------------- this change shows as "X red colored waveform"
                                       
                when others =>
            end case;
        end if;
    end if;
    
end process KpDebounce;   

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richardhead
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1,174 Views
Registered: ‎08-01-2012

Ok, so the only answer here is to use a shared variable. What do you expect to happen when both processes write to the same address at the same time? The VHDL shows the correct behaviour with XXXs, as it has no idea which signal wins, so you will get XXX.

 

A shared variable will avoid the Xs, but you are at the mercy of a race condition on a write to both locations at the same time.

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