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kp1998_
Participant
Participant
449 Views
Registered: ‎06-11-2019

Array

Hello

For a given condition i want to store few values of a given array into another array but it is shwoing error. Please help with this.
Error it is showing is - 

ERROR: [VRFC 10-1243] port array1 must not be declared to be an array [D:/Prog/butterworth_filter/butterworth_filter.srcs/sources_1/new/median_filter.v:51]
ERROR: [VRFC 10-1040] module median_filter ignored due to previous errors [D:/Prog/butterworth_filter/butterworth_filter.srcs/sources_1/new/median_filter.v:21]

Thank you

Regards

Neha

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5 Replies
dror_m
Observer
Observer
436 Views
Registered: ‎06-19-2019

please share the code
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rshekhaw
Xilinx Employee
Xilinx Employee
429 Views
Registered: ‎05-22-2018

Hi @kp1998_ ,

Please check this AR# link:

https://www.xilinx.com/support/answers/52934.html

Thanks,

Raj

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kp1998_
Participant
Participant
413 Views
Registered: ‎06-11-2019

Hello i am sharing a part of my code -

reg [7:0]dat0,dat1,dat2,dat3,dat4,dat5,dat6,dat7,dat8;
always @(posedge clk)
begin
dat0 <= A0;
dat1 <= A1;
dat2 <= A2;
dat3 <= A3;
dat4 <= A4;
dat5 <= A5;
dat6 <= A6;
dat7 <= A7;
dat8 <= A8;
end
integer i,j;
reg [7:0]temp;
reg [7:0]array[0:8];
output reg [7:0]array1[0:8];
always @*
begin
array[0] = dat0;
array[1] = dat1;
array[2] = dat2;
array[3] = dat3;
array[4] = dat4;
array[5] = dat5;
array[6] = dat6;
array[7] = dat7;
array[8] = dat8;
for (i = 9; i > 0; i = i - 1) begin
for (j = 0 ; j < i; j = j + 1) begin
if (array[j] > array[j + 1])
begin
temp = array[j];
array[j] = array[j + 1];
array[j + 1] = temp;
end
end
end
end
always @(posedge clk)
begin
out0 <= array[0];
out1 <= array[1];
out2 <= array[2];
out3 <= array[3];
out4 <= array[4];
out5 <= array[5];
out6 <= array[6];
out7 <= array[7];
out8 <= array[8];
end
genvar k;
generate
for (k = 0;k < 9;k = k + 1) begin
always@(posedge clk)begin
if(array[k]!=0 && array[k]!=255)
array1[k]<=array[k];
end
end
endgenerate

Can you please check and tell whether its correct or not.
Thank you
Regards
Neha
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kp1998_
Participant
Participant
408 Views
Registered: ‎06-11-2019

Hello
How to convert the existing verilog code to system verilog in vivado software.
Is it possible to find length of one dimensional array using verilog.
Please help with this.
Thank you
Regards
Neha
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dror_m
Observer
Observer
378 Views
Registered: ‎06-19-2019

there are 2 easy ways to covert the code to sv:
1. change the suffix to sv instead of v.
2. in the vivado, click the file and the in the properties check the checkbox of system verilog.