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Scholar helmutforren
Scholar
3,076 Views
Registered: ‎06-23-2014

Arrays of Interfaces?

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I'm using Vivado 2017.1 and SystemVerilog.

 

The post at https://forums.xilinx.com/t5/Synthesis/When-will-Vivado-support-SystemVerilog-interface-arrays/td-p/529351 suggests that, for SYNTHESIS at least, arrays of interfaces are supported since 2015, in spite of the out-of-date AR 55135 .

 

(Note that SYNTHSIS *also* gives errors like "[Synth 8-146] cannot resolve hiearchical name".)

 

However, when I try to SIMULATE an array of interfaces, I get what I'll call parsing errors.  Specifically, this code:

    `define NUMBER_OF_BINS  (128)

    genvar gen_index;
    
    i_HE_fifo HE_sort_bin[`NUMBER_OF_BINS]();    // Instance the interface

    for (gen_index=0; gen_index<=`NUMBER_OF_BINS; gen_index=gen_index+1) begin
        FIFO_HE_sort_bin HE_sort_bin_FIFO (
            .rst(rst0),
            .clk(clk),
            .din(HE_sort_bin[gen_index].push_data),
            .wr_en(HE_sort_bin[gen_index].wr_en),
            .rd_en(HE_sort_bin[gen_index].rd_en),
            .dout(HE_sort_bin[gen_index].pop_data),
            .full(HE_sort_bin[gen_index].full),
            .prog_full(HE_sort_bin[gen_index].prog_full),
            .empty(HE_sort_bin[gen_index].empty)
        );
    
        // TEMPORARY TESTING ONLY
        always @(posedge clk) begin
            HE_sort_bin[gen_index].rd_en <= 1;  // BURN ALL ENTRIES
        end
    end

gets the errors

SIMULATION ERRORS:

ERROR: [VRFC 10-93] rd_en is not declared under prefix HE_sort_bin [M:/MyProject/MyProject.srcs/sources_1/new/Histogram_Equalization.sv:102]
ERROR: [VRFC 10-93] push_data is not declared under prefix HE_sort_bin [M:/MyProject/MyProject.srcs/sources_1/new/Histogram_Equalization.sv:91]
ERROR: [VRFC 10-93] wr_en is not declared under prefix HE_sort_bin [M:/MyProject/MyProject.srcs/sources_1/new/Histogram_Equalization.sv:92]
ERROR: [VRFC 10-93] rd_en is not declared under prefix HE_sort_bin [M:/MyProject/MyProject.srcs/sources_1/new/Histogram_Equalization.sv:93]
ERROR: [VRFC 10-93] pop_data is not declared under prefix HE_sort_bin [M:/MyProject/MyProject.srcs/sources_1/new/Histogram_Equalization.sv:94]
ERROR: [VRFC 10-93] full is not declared under prefix HE_sort_bin [M:/MyProject/MyProject.srcs/sources_1/new/Histogram_Equalization.sv:95]
ERROR: [VRFC 10-93] prog_full is not declared under prefix HE_sort_bin [M:/MyProject/MyProject.srcs/sources_1/new/Histogram_Equalization.sv:96]
ERROR: [VRFC 10-93] empty is not declared under prefix HE_sort_bin [M:/MyProject/MyProject.srcs/sources_1/new/Histogram_Equalization.sv:97]

but if I simply remove the "for" and hard code the index to some middle value, such as 12:

    `define NUMBER_OF_BINS  (128)

    genvar gen_index;
    
    i_HE_fifo HE_sort_bin[`NUMBER_OF_BINS]();    // Instance the interface

//    for (gen_index=0; gen_index<=`NUMBER_OF_BINS; gen_index=gen_index+1) begin
        FIFO_HE_sort_bin HE_sort_bin_FIFO (
            .rst(rst0),
            .clk(clk),
            .din(HE_sort_bin[12].push_data),
            .wr_en(HE_sort_bin[12].wr_en),
            .rd_en(HE_sort_bin[12].rd_en),
            .dout(HE_sort_bin[12].pop_data),
            .full(HE_sort_bin[12].full),
            .prog_full(HE_sort_bin[12].prog_full),
            .empty(HE_sort_bin[12].empty)
        );
    
        // TEMPORARY TESTING ONLY
        always @(posedge clk) begin
            HE_sort_bin[12].rd_en <= 1;  // BURN ALL ENTRIES
        end
//    end

the parsing errors go away and simulation is ready for me to run.  (I have not yet subsequently run it and tested for expected behavior.)

 

Note that the interface and structures are defined as

typedef struct packed { // 42 BITS
    logic [20:0] tuple_key;     //      [41:21] Tuple Key
    logic [20:0] tuple_data;    //      [20:00] Tuple Data
} t_HE_fifo_word;

interface i_HE_fifo;    
    t_HE_fifo_word push_data;
    logic wr_en;
    logic full;
    logic prog_full;

    t_HE_fifo_word pop_data;
    logic rd_en;
    logic empty;
    
    modport push (
        input full,
        input prog_full,
        output wr_en,
        output push_data
    );
    
    modport pop (
        input empty,
        output rd_en,
        input pop_data
    );
    
    modport ila (
        input full,
        input prog_full,
        input wr_en,
        input push_data,
        input empty,
        input rd_en,
        input pop_data
    );
endinterface
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1 Solution

Accepted Solutions
Moderator
Moderator
4,132 Views
Registered: ‎04-24-2013

Re: Arrays of Interfaces?

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Hi @helmutforren,

 

Unfortunately Array of Interface in SystemVerilog is not supported by Synthesis at this time.

 

This is documented in Chapter 8 of User Guide 901.

 

There has been some work done to improve this and certain constructs may work in later versions of the tools but it is not currently supported.

 

Capture1.PNG

 

Let me know if this helps.

Best Regards
Aidan

 

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4 Replies
Explorer
Explorer
3,058 Views
Registered: ‎03-31-2016

Re: Arrays of Interfaces?

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You seem to be missing the generate keyword.   You should also name your generate blocks, most tools give a warning about unnamed generate blocks.

 

generate

      for(   ....  ) : GEN_NAME

         ...

      end

endgenerate

 

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Scholar helmutforren
Scholar
3,040 Views
Registered: ‎06-23-2014

Re: Arrays of Interfaces?

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Nope.

 

Thanks very much, sincerely.  That was a dumb error.  But fixing it didn't fix the problem.  Same errors.

 

-Helmut

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Moderator
Moderator
4,133 Views
Registered: ‎04-24-2013

Re: Arrays of Interfaces?

Jump to solution

Hi @helmutforren,

 

Unfortunately Array of Interface in SystemVerilog is not supported by Synthesis at this time.

 

This is documented in Chapter 8 of User Guide 901.

 

There has been some work done to improve this and certain constructs may work in later versions of the tools but it is not currently supported.

 

Capture1.PNG

 

Let me know if this helps.

Best Regards
Aidan

 

------------------------------------------------------------------------------------------------------------------
Please mark the Answer as "Accept as solution" if this answered your question
Give Kudos to a post which you think is helpful and may help other users
------------------------------------------------------------------------------------------------------------------
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Visitor amol_aeva
Visitor
2,693 Views
Registered: ‎01-23-2018

Re: Arrays of Interfaces?

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I'm using 2017.4 and though UG901 says that Array of Interfaces is Not Supported, I have been successfully using 1D arrays for a while now. 

Example:

bus my_bus[2] ();

 

However when I try to generate a 2D array of interfaces it fails in Elaboration.

bus my_bus[2][2] ();

 

Any idea when this will be supported?

Attached a test case to show this.

 

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