I'm using Vivado 2017.1 and SystemVerilog.
The post at https://forums.xilinx.com/t5/Synthesis/When-will-Vivado-support-SystemVerilog-interface-arrays/td-p/529351 suggests that, for SYNTHESIS at least, arrays of interfaces are supported since 2015, in spite of the out-of-date AR 55135 .
(Note that SYNTHSIS *also* gives errors like "[Synth 8-146] cannot resolve hiearchical name".)
However, when I try to SIMULATE an array of interfaces, I get what I'll call parsing errors. Specifically, this code:
`define NUMBER_OF_BINS (128)
genvar gen_index;
i_HE_fifo HE_sort_bin[`NUMBER_OF_BINS](); // Instance the interface
for (gen_index=0; gen_index<=`NUMBER_OF_BINS; gen_index=gen_index+1) begin
FIFO_HE_sort_bin HE_sort_bin_FIFO (
.rst(rst0),
.clk(clk),
.din(HE_sort_bin[gen_index].push_data),
.wr_en(HE_sort_bin[gen_index].wr_en),
.rd_en(HE_sort_bin[gen_index].rd_en),
.dout(HE_sort_bin[gen_index].pop_data),
.full(HE_sort_bin[gen_index].full),
.prog_full(HE_sort_bin[gen_index].prog_full),
.empty(HE_sort_bin[gen_index].empty)
);
// TEMPORARY TESTING ONLY
always @(posedge clk) begin
HE_sort_bin[gen_index].rd_en <= 1; // BURN ALL ENTRIES
end
end
gets the errors
SIMULATION ERRORS:
ERROR: [VRFC 10-93] rd_en is not declared under prefix HE_sort_bin [M:/MyProject/MyProject.srcs/sources_1/new/Histogram_Equalization.sv:102]
ERROR: [VRFC 10-93] push_data is not declared under prefix HE_sort_bin [M:/MyProject/MyProject.srcs/sources_1/new/Histogram_Equalization.sv:91]
ERROR: [VRFC 10-93] wr_en is not declared under prefix HE_sort_bin [M:/MyProject/MyProject.srcs/sources_1/new/Histogram_Equalization.sv:92]
ERROR: [VRFC 10-93] rd_en is not declared under prefix HE_sort_bin [M:/MyProject/MyProject.srcs/sources_1/new/Histogram_Equalization.sv:93]
ERROR: [VRFC 10-93] pop_data is not declared under prefix HE_sort_bin [M:/MyProject/MyProject.srcs/sources_1/new/Histogram_Equalization.sv:94]
ERROR: [VRFC 10-93] full is not declared under prefix HE_sort_bin [M:/MyProject/MyProject.srcs/sources_1/new/Histogram_Equalization.sv:95]
ERROR: [VRFC 10-93] prog_full is not declared under prefix HE_sort_bin [M:/MyProject/MyProject.srcs/sources_1/new/Histogram_Equalization.sv:96]
ERROR: [VRFC 10-93] empty is not declared under prefix HE_sort_bin [M:/MyProject/MyProject.srcs/sources_1/new/Histogram_Equalization.sv:97]
but if I simply remove the "for" and hard code the index to some middle value, such as 12:
`define NUMBER_OF_BINS (128)
genvar gen_index;
i_HE_fifo HE_sort_bin[`NUMBER_OF_BINS](); // Instance the interface
// for (gen_index=0; gen_index<=`NUMBER_OF_BINS; gen_index=gen_index+1) begin
FIFO_HE_sort_bin HE_sort_bin_FIFO (
.rst(rst0),
.clk(clk),
.din(HE_sort_bin[12].push_data),
.wr_en(HE_sort_bin[12].wr_en),
.rd_en(HE_sort_bin[12].rd_en),
.dout(HE_sort_bin[12].pop_data),
.full(HE_sort_bin[12].full),
.prog_full(HE_sort_bin[12].prog_full),
.empty(HE_sort_bin[12].empty)
);
// TEMPORARY TESTING ONLY
always @(posedge clk) begin
HE_sort_bin[12].rd_en <= 1; // BURN ALL ENTRIES
end
// end
the parsing errors go away and simulation is ready for me to run. (I have not yet subsequently run it and tested for expected behavior.)
Note that the interface and structures are defined as
typedef struct packed { // 42 BITS
logic [20:0] tuple_key; // [41:21] Tuple Key
logic [20:0] tuple_data; // [20:00] Tuple Data
} t_HE_fifo_word;
interface i_HE_fifo;
t_HE_fifo_word push_data;
logic wr_en;
logic full;
logic prog_full;
t_HE_fifo_word pop_data;
logic rd_en;
logic empty;
modport push (
input full,
input prog_full,
output wr_en,
output push_data
);
modport pop (
input empty,
output rd_en,
input pop_data
);
modport ila (
input full,
input prog_full,
input wr_en,
input push_data,
input empty,
input rd_en,
input pop_data
);
endinterface
