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Visitor
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Registered: ‎06-04-2020

Artix 7 maximum IO toggling frequency

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Hi,

Based on Artix 7 series XC7A200TFBG484-2 fpga.

i am trying to figure out the maximum IO toggling frequency.

it is found that the toggling frequency is less than 200MHz.

is it an expected behavior?

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Teacher
Teacher
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Registered: ‎07-09-2009
your right, if you have set the pin to LVCMOS33, depending upon the strength, is how fast the IO can change.

BUT

I assume your just using the led pins as you have them on your design as IO, not that your trying to see a led flash.

What you must remember, is even if the IO can toggle in 4 ns, if it takes a signal 10 ns to get to the IOB, then you are not going to get a fit.

Register the outputs a few times, do not use clear or anything , just register, and see what that does.

BTW: Who ever teaches you to use clk'event, should be shot
use elsif rising_edge( clk ) then

Also, look at the libraries you have, as you are adding 1 to what I guess is a std_logic_vector, I'm betting your using std_logic_arith, who ever told you to use that should also be shot.....

https://www.nandland.com/articles/std_logic_arith_vs_numeric_std.html


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Registered: ‎06-21-2017

How are you trying to determine this? 

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Scholar
Scholar
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Registered: ‎08-07-2014

@sinya,

i am trying to figure out the maximum IO toggling frequency.

As far as I know the the max freq is limited by the capabilities of the clock buffers.

Did you look in to the A7 datasheet? It is mentioned in there that IO pins have freq limitation?

All I know is that the IO pins have restriction as per voltage levels. But I may be wrong, please cross check.

------------FPGA enthusiast------------
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Teacher
Teacher
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Registered: ‎07-09-2009
Timing in FPGAs is dependent upon the circuit you build.

What you need to do is do a test design, with timing constraints and see what you get .

this is the AC data sheet
https://www.xilinx.com/support/documentation/data_sheets/ds181_Artix_7_Data_Sheet.pdf

if you look at say page 16, it shows you the different pad speeds for each of the different speed grades, and types of signal ,

But to that you have to add the time for your circuit,
if you have a lot of gates between the last register and the pad, then its going to be slower than if you used a register in the IOB.

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Registered: ‎06-04-2020

@dpaul24,

i am using following code the:

-----------Code-------------

process (i_rst_n,clk_200mhz)
begin
if(i_rst_n = '0') then
four_bit_counter_num <= "0000";
elsif (clk_200mhz'event and clk_200mhz = '1') then
four_bit_counter_num (3 downto 0) <= four_bit_counter_num (3 downto 0) + 1;
end if;
end process four_bit_counter_process;

led <= four_bit_counter_num (3);

---------Constraint---------------

set_property PACKAGE_PIN R19 [get_ports led]

set_property IOSTANDARD LVCMOS33 [get_ports led]

create_clock -period 5.000 -name clk_200mhz -waveform {0.000 2.50} [get_ports clk_200mhz]

set_output_delay -clock [get_clocks clk_200mhz] -max 1.000 [get_ports led]

set_output_delay -clock [get_clocks clk_200mhz] -min 0 [get_ports led]

---------------------

with the output delay constraint, the negative slack can be observed. even though change to

set_output_delay -clock [get_clocks clk_200mhz] -max 0.000 [get_ports led].

the negative slack is still there.

if reducing the constraint frequency to 50mhz, 100mhz. positive slack comes .

about the OBUF delay, from OBUF_I to OBUF_O, it takes about 3.426ns.

that is why i thought IO switching frequency has a limitation.

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Visitor
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Registered: ‎06-04-2020

@drjohnsmith,

refer to attachment, as i understand, the red area should be the reference value.

is it correct?

AC.png
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Scholar
Scholar
273 Views
Registered: ‎08-07-2014

@sinya,

led <= four_bit_counter_num (3);

It makes no sense to assign values changing at the rate of 200M to LEDs. Human eyes will not be able to track the changes.

If your target is to display the changes of the counter values to LEDs then you need to use a much lower clock, and if you do that there won't be any -ive slack. You also will have no problems with freq of IO pins.

------------FPGA enthusiast------------
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer has solved your problem

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Highlighted
Teacher
Teacher
251 Views
Registered: ‎07-09-2009
your right, if you have set the pin to LVCMOS33, depending upon the strength, is how fast the IO can change.

BUT

I assume your just using the led pins as you have them on your design as IO, not that your trying to see a led flash.

What you must remember, is even if the IO can toggle in 4 ns, if it takes a signal 10 ns to get to the IOB, then you are not going to get a fit.

Register the outputs a few times, do not use clear or anything , just register, and see what that does.

BTW: Who ever teaches you to use clk'event, should be shot
use elsif rising_edge( clk ) then

Also, look at the libraries you have, as you are adding 1 to what I guess is a std_logic_vector, I'm betting your using std_logic_arith, who ever told you to use that should also be shot.....

https://www.nandland.com/articles/std_logic_arith_vs_numeric_std.html


<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

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244 Views
Registered: ‎06-21-2017

@drjohnsmith , running low on patience on a Friday afternoon?  Shot is pretty extreme.  How about just tar and feathers?

To get back on topic, the proper way to drive a clock out of an FPGA is to use a DDR output register.  Set one data input pin high, the other data input pin low.  Run the clock to the register and you have lower skew, since the clock never leaves dedicated clocking resources and the timing is more consistent since the register is right at the output.

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Visitor
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Registered: ‎06-04-2020

@drjohnsmith, @dpaul24 ,@bruce_karaffa ,

thanks for your help on this topic.

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