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Observer mreisteremp
Observer
11,452 Views
Registered: ‎03-17-2014

Assigned Top Level simulation file Vivado

I am attempting to simulate a vivado ip project. What I would like to do is create a top level file that calls my design. I have created this top levels file and “added it” to my simulation set. However, when I add this to my simulation set it get place into a “unreferenced” file location under libraries in vivado? (see attached screenshot)

 

I guess this get placed in the unreferenced file location because nothing is referencing it…. But how do I tell vivado that this is the top level file I would like to use for my simulation?

 

I tried right clicking on the file I would like to make my top level simulation source and try to make it my top level module however when i do this i dont see and option for setting this as a top level module

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VivadoSimulationQuestion.PNG
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3 Replies
Xilinx Employee
Xilinx Employee
11,448 Views
Registered: ‎02-16-2014

Re: Assigned Top Level simulation file Vivado

Hi,

 

Have tried setting it as top module from sources tab?

Check below.

 

In the source Tab -> Select the file which you need to set as top module from the simulation Sources -> right Click on it -> Set as Top Module

Untitled.png

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Xilinx Employee
Xilinx Employee
11,433 Views
Registered: ‎09-20-2012

Re: Assigned Top Level simulation file Vivado

Hi,

 

Do you see any errors in console?

 

Thanks,

Deepika.

Thanks,
Deepika.
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Observer mreisteremp
Observer
11,413 Views
Registered: ‎03-17-2014

Re: Assigned Top Level simulation file Vivado

ok thanks for the replay, but the problem was that there was errors in the Top level file that i wanted to use. Once i corrected this error it poped into my simulation section and was able to use it as my top level simulation file.... my bad.

 

However, i never recieved any errors about this file i had to find the and correct the errors in the file by inspecting it myself.....

 

I am now having almost the exact same problem now with a diffrent file. Maybe i should open a new thread on this, but I am trying to add a vhdl library to my simulation and it throws this package into the exact same place the "unrefrenced" seciton.  I do refrence this library in my simulation so agian i dont understand why it states it non-refrenced.... 

 

I am assuming the probablem is the same. The package i am trying to add has errors in it and that is why vivado thinks its unrefrenced.

 

However i dont know anyway way to "check syntax" on this file. ISE had a check syntax button, but this seams to be missing in vivado.. 

 

So what is the best way to find the syntax errors in a file that vivado thinks is unrefrenced?

 

I have attached a screenshot of my new unrefrenced file...

 

 

Axi_Stim_Error.PNG
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