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Participant
Participant
606 Views
Registered: ‎02-26-2013

Automatic verification resources

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Hello,

I need to do some jobs in the core verification/test bench, but I'm not sure how.

-measure delay between assertion of two internal signals in the DUT

- record the data into file - for example AXI Stream bus data

I can use the TCL or VHDL test bench. From VHDL, I don't know if possible to access on the internal signals in DUT.

Thank you

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Scholar
Scholar
584 Views
Registered: ‎08-01-2012

Re: Automatic verification resources

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Vhdl 2008 has external names, so you can access any object from anywhere in the vhdl.

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Scholar
Scholar
585 Views
Registered: ‎08-01-2012

Re: Automatic verification resources

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Vhdl 2008 has external names, so you can access any object from anywhere in the vhdl.

View solution in original post

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Participant
Participant
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Registered: ‎02-26-2013

Re: Automatic verification resources

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Thank you!

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531 Views
Registered: ‎01-22-2015

Re: Automatic verification resources

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@petr_

Using the Vivado simulator, it is possible to plot waveforms for signals that are internal to the DUT(UUT). For more information, see the section called “Scopes Window” on about page 53 of UG900.

Mark

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