UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer petr_
Observer
272 Views
Registered: ‎02-26-2013

Automatic verification resources

Jump to solution

Hello,

I need to do some jobs in the core verification/test bench, but I'm not sure how.

-measure delay between assertion of two internal signals in the DUT

- record the data into file - for example AXI Stream bus data

I can use the TCL or VHDL test bench. From VHDL, I don't know if possible to access on the internal signals in DUT.

Thank you

0 Kudos
1 Solution

Accepted Solutions
Scholar richardhead
Scholar
250 Views
Registered: ‎08-01-2012

Re: Automatic verification resources

Jump to solution

Vhdl 2008 has external names, so you can access any object from anywhere in the vhdl.

3 Replies
Scholar richardhead
Scholar
251 Views
Registered: ‎08-01-2012

Re: Automatic verification resources

Jump to solution

Vhdl 2008 has external names, so you can access any object from anywhere in the vhdl.

Highlighted
Observer petr_
Observer
211 Views
Registered: ‎02-26-2013

Re: Automatic verification resources

Jump to solution

Thank you!

0 Kudos
197 Views
Registered: ‎01-22-2015

Re: Automatic verification resources

Jump to solution

@petr_

Using the Vivado simulator, it is possible to plot waveforms for signals that are internal to the DUT(UUT). For more information, see the section called “Scopes Window” on about page 53 of UG900.

Mark

0 Kudos