01-18-2019 01:28 PM
I need to do some jobs in the core verification/test bench, but I'm not sure how.
-measure delay between assertion of two internal signals in the DUT
- record the data into file - for example AXI Stream bus data
I can use the TCL or VHDL test bench. From VHDL, I don't know if possible to access on the internal signals in DUT.
01-19-2019 04:56 AM
Using the Vivado simulator, it is possible to plot waveforms for signals that are internal to the DUT(UUT). For more information, see the section called “Scopes Window” on about page 53 of UG900.