cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Participant
Participant
705 Views
Registered: ‎02-26-2013

Automatic verification resources

Jump to solution

Hello,

I need to do some jobs in the core verification/test bench, but I'm not sure how.

-measure delay between assertion of two internal signals in the DUT

- record the data into file - for example AXI Stream bus data

I can use the TCL or VHDL test bench. From VHDL, I don't know if possible to access on the internal signals in DUT.

Thank you

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Scholar
Scholar
683 Views
Registered: ‎08-01-2012

Vhdl 2008 has external names, so you can access any object from anywhere in the vhdl.

View solution in original post

3 Replies
Highlighted
Scholar
Scholar
684 Views
Registered: ‎08-01-2012

Vhdl 2008 has external names, so you can access any object from anywhere in the vhdl.

View solution in original post

Highlighted
Participant
Participant
644 Views
Registered: ‎02-26-2013

Thank you!

0 Kudos
Highlighted
630 Views
Registered: ‎01-22-2015

@petr_

Using the Vivado simulator, it is possible to plot waveforms for signals that are internal to the DUT(UUT). For more information, see the section called “Scopes Window” on about page 53 of UG900.

Mark

0 Kudos