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Visitor phil_0031
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Registered: ‎09-19-2018

BRAM initialization for Post-Synthesis simulation

I have integrated in Vivado a SW core having internal scratch-pad RAM for data (dspm) and instruction (ispm), synthesize as BRAM ressource on the Arty Z7-10 (xc7z010clg400-1).

The memory is implemented in verilog as following, to match BRAMS allocation (16Kb) using generate and BRAMS directive.

For functional simulation, I have created a verilog testbench with following initialization (defining the hiearchy for initialisation). Simulation works.

  reg [31:0] ispm_init [4095:0];
  reg [31:0] dspm_init [4095:0];
  reg [15:0] k; 

   $readmemh("ispmfile.mem", ispm_init);
    $readmemh("dspmfile.mem", dspm_init);
    for(k = 0; k < 4096; k = k + 1) begin
        design_system_1.design_1_i.Core_0.inst.imem.BRAMS[0].ispm[k] = ispm_init[k][3:0];
        design_system_1.design_1_i.Core_0.inst.imem.BRAMS[1].ispm[k] = ispm_init[k][7:4];
  

I want to reuse the same testbench after synthesis for post-synthesis functional simualtion, and get the following error:

ERROR: [VRFC 10-93] BRAMS is not declared under prefix imem.

I have checked names in synthesize netlist hiearchy (and also in schematic) design_system_1.design_1_i.Core_0.inst.imem.BRAMS[0].ispm_reg exist and even by using this name, I get the same error indefined imem.

What's wrong ?

Thanks for help

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