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303 Views
Registered: ‎02-21-2019

BUFGCE output low in post-implementation simulation

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I am trying to do a post-implementation timing simulation on a design using Modelsim.

I managed to get the libraries and the netlist compiled and start the simulation. However, one of the BUFGCEs at the edge of the design seems to just output a low, causing nothing else to work. The screenshot below shows the instantiation in the generated netlist:

Screenshot_3.png

I used the following commands to generate the netlist and the sdf files:

 

write_verilog -force -mode timesim -sdf_anno true -rename_top lvds_ti_ultra96_top -sdf_file impl_timing_sim.sdf impl_timing_sim.v
write_sdf -force -rename_top lvds_ti_ultra96_top impl_timing_sim.sdf

In the simulation, i can see that the input to BUFGCE bitclk_in_buf_0 behaves as expected. But the output bitclk_in is always low. (I start the simulation after waiting for 100 ns initially as well).Screenshot_4.png

 

Note: bitclk_in_buf_0 is the output of an IBUFDS, to which bitclk_in_p and bitclk_in_n are inputs:Screenshot_5.png

 

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Xilinx Employee
Xilinx Employee
218 Views
Registered: ‎07-16-2008

回复: BUFGCE output low in post-implementation simulation

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From the SDF,

(CELL
(CELLTYPE "BUFGCE")
(INSTANCE lvds_bit_clk_sync_inst/bufg_bitclk_routing_inst0)
(DELAY
(PATHPULSEPERCENT (30.0))
(ABSOLUTE
(IOPATH I O (24.0:28.0:28.0) (24.0:28.0:28.0))
)
)

The pulse rejection limit is specified as 30% of the delay time from input to output. If your pulse width is smaller than 28*30%=8.4ps, it will not propagate through the buffer.

 

Please add the following switches to vsim command to ensure proper timing simulation.

+transport_int_delays +pulse_int_e/0 +pulse_int_r/0

 

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Don't forget to reply, kudo, and accept as solution.
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3 Replies
Xilinx Employee
Xilinx Employee
275 Views
Registered: ‎07-16-2008

回复: BUFGCE output low in post-implementation simulation

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What is the clock frequency? Can you post the SDF as well as the command you run the post-implementation timing simulation in Modelsim?

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Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
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250 Views
Registered: ‎02-21-2019

回复: BUFGCE output low in post-implementation simulation

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Hi,

I have attached the SDF file and the do file used for the simulation.

Sorry i had to zip the two files because it complained about content type not matching the file extensions.

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Xilinx Employee
Xilinx Employee
219 Views
Registered: ‎07-16-2008

回复: BUFGCE output low in post-implementation simulation

Jump to solution

From the SDF,

(CELL
(CELLTYPE "BUFGCE")
(INSTANCE lvds_bit_clk_sync_inst/bufg_bitclk_routing_inst0)
(DELAY
(PATHPULSEPERCENT (30.0))
(ABSOLUTE
(IOPATH I O (24.0:28.0:28.0) (24.0:28.0:28.0))
)
)

The pulse rejection limit is specified as 30% of the delay time from input to output. If your pulse width is smaller than 28*30%=8.4ps, it will not propagate through the buffer.

 

Please add the following switches to vsim command to ensure proper timing simulation.

+transport_int_delays +pulse_int_e/0 +pulse_int_r/0

 

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
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