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esakki@babu
Adventurer
Adventurer
586 Views
Registered: ‎11-09-2018

BUFR clock alignment

Hi

I tried to simulate the below code, here Input clock clk_in_int_delay give to BUFR. please see the simulation result. clk_by_2_reg it showing red color and the value is "X". Please help this. 

module clk_reg(
input reset,
input clk_in_int_delay
);

reg clk_by_2_reg;

BUFR
#(.SIM_DEVICE("7SERIES"),
.BUFR_DIVIDE("5"))
clkout_buf_inst
(.O (clk_div),
.CE(1'b1),
.CLR(reset),
.I (clk_in_int_delay));

always @(posedge clk_div)
if (reset) begin
clk_by_2_reg <= 1'b0;
end else begin
clk_by_2_reg <= ~clk_by_2_reg;
end
endmodule

 

q1.JPG

Thanks 

Esakki

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7 Replies
joancab
Advisor
Advisor
579 Views
Registered: ‎05-11-2015

In your testbench file, you need to reset the process for a couple of cycles to set an initial value to clk_by_2_reg.

Otherwise it's unknown (X) and every time you toggle it, is also unknown.

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esakki@babu
Adventurer
Adventurer
572 Views
Registered: ‎11-09-2018

@joancab 

Yes,  initially I reset the process during simulation I gave value for reset is 1 then I changed to 0.  Please see the below simulation. 

reply1q1.JPG

 

and also please see the below simulation without using BUFR 

module clk_reg(
input reset,
input clk_in_int_delay
);

reg clk_by_2_reg;

always @(posedge clk_in_int_delay)
if (reset) begin
clk_by_2_reg <= 1'b0;
end else begin
clk_by_2_reg <= ~clk_by_2_reg;
end
endmodule

reply2q1.JPG

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esakki@babu
Adventurer
Adventurer
563 Views
Registered: ‎11-09-2018

Please help this above thread. 

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joancab
Advisor
Advisor
537 Views
Registered: ‎05-11-2015

Voilà:

joancab_0-1616843904957.png

You need to change your process like this:

always @(posedge reset, posedge clk_div)
    if (reset) begin
        clk_by_2_reg <= 1'b0;
    end else begin
        clk_by_2_reg <= ~clk_by_2_reg;
    end
endmodule

The reason is as it was written before reset still needed a clk_div edge, but reset was clearing BUFR so there was no clk_div and clk_by_2_reg was never reset.

You may need to refine the reset condition

430 Views
Registered: ‎01-22-2015

esakki@babu 

Joan has helped you solve the simulation "X" problem.  However, there are strict rules for BUFR clock alignment in 7-Series devices.  These rules are described on pg110 of UG472(v1.14), but Avrum and I believe they are incorrect.  Please see the following post for more on BUFR clock alignment.

https://forums.xilinx.com/t5/Other-FPGA-Architecture/Multiple-region-BUFR-alignment/m-p/1062626#M37596

Cheers,
Mark

esakki@babu
Adventurer
Adventurer
264 Views
Registered: ‎11-09-2018

Is It possible to Debug CLOCK like BUFMRC out, BUFR out, BUFIO out using ILA? How to do? As of know, I simulate the clock by force clock in nano seconds that depends on my design.

for eg. 50MHz input clock I used 20ns or  40MHz input clock I used 40ns.

 

Thanks

Esakki

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joancab
Advisor
Advisor
258 Views
Registered: ‎05-11-2015

I'm not sure if ILA will take a clock as a signal. All you need is a faster clock (min double frequency) and you can capture 1s and 0s.

I just wonder why. Clocks are in many cases generated in MMCMs and PLLs from a known external clock from an oscillator. These are pieces you can trust.

 

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