10-15-2013 08:04 AM
When I instantiate a BUFR in a file and use the output clock in a FFD, if I use the output of the FFD in another file as input to a FFD using the same BUFR clock, the simulation does not work as expected.
If everything is in the same file or I do a translate simulation, the result is as expected.
10-15-2013 12:35 PM
10-15-2013 11:04 PM
Thanks for the reply.
All the flip flops have the same clock as can be seen in the attached VHDL code. I also thnough it was a race condition but even in the RTL viewer it can be seen that all the elements have the same clock.
10-16-2013 09:37 AM
10-16-2013 11:00 PM