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Observer jesuslazaro
Observer
4,184 Views
Registered: ‎02-25-2013

BUFR simulation error when not in the same file using ISIM

When I instantiate a BUFR in a file and use the output clock in a FFD, if I use the output of the FFD in another file as input to a FFD using the same BUFR clock, the simulation does not work as expected.

 

If everything is in the same file or I do a translate simulation, the result is as expected.

 

 

 

bufr_error.jpg

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4 Replies
Teacher muzaffer
Teacher
4,180 Views
Registered: ‎03-31-2012

Re: BUFR simulation error when not in the same file using ISIM

I think you are seeing a race condition based on two different clocks being in use. You can't observe it in the waveform because the clocks happen at the same time but at different simulation steps. I am not exactly sure how to fix it in VHDL but try generating your clock at a higher level and make it pass through the same number of module (entity) boundaries; that might help.
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Observer jesuslazaro
Observer
4,167 Views
Registered: ‎02-25-2013

Re: BUFR simulation error when not in the same file using ISIM

Hello,

 

Thanks for the reply.

 

All the flip flops have the same clock as can be seen in the attached VHDL code. I also thnough it was a race condition but even in the RTL viewer it can be seen that all the elements have the same clock.

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Teacher muzaffer
Teacher
4,159 Views
Registered: ‎03-31-2012

Re: BUFR simulation error when not in the same file using ISIM

I don't see an attached VHDL file.
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Observer jesuslazaro
Observer
4,150 Views
Registered: ‎02-25-2013

Re: BUFR simulation error when not in the same file using ISIM

In the original post there is a ZIP file with three VHDL files, including the testbench used to generate the image.
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