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Observer nebenni
Observer
709 Views
Registered: ‎05-08-2018

[BUG report] VHDL: type natural accepts negative values

Hello Xilinx-Developers, i found yet another bug:

The type natural is defined as

subtype Natural is Integer range 0 to Integer'high;

However, even in some simple cases, vivado seems to ignore the range-constraint completely.

I have created a minimal example for you to investigate:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity example is
end example;

architecture Behavioral of example is
	signal clk : std_logic := '0';

	procedure demoproc(constant numberOfCells : in natural range 0 to 255) is
	begin
		report "called demoproc, numberOfCells is "&natural'IMAGE(numberOfCells) severity note;
	end procedure;
begin
	clk <= not clk after 50 ns;
        process(clk) -- no errors??
		variable cycle : natural := 0;
	begin
		if rising_edge(clk) then
			cycle := cycle + 1;
			case cycle is
				when 0 =>
					demoproc(-42);
				when 1 to 7 =>
					demoproc(cycle-4);
				when others =>
					null;
					cycle := -1000; -- no errors??!
			end case;
		end if;
	end process;
end Behavioral;

When this file is run in simulation, no errors are thrown, despite

  • negative numbers beeing passed to demoproc, which only accepts natural values
  • a negative number (-1000) beeing assigned to the variable cycle

This also happens in processes with a sensitivity list and "rising_edge(clk)", however it seems harder to demonstrate the bug with a minimal example in this case - if i have time i might post another example for this...

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14 Replies
Observer nebenni
Observer
644 Views
Registered: ‎05-08-2018

Re: [BUG report] VHDL: type natural accepts negative values

Any statement from xilinx?

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Scholar drjohnsmith
Scholar
635 Views
Registered: ‎07-09-2009

Re: [BUG report] VHDL: type natural accepts negative values

In my experiance XiIinx putup with VHDL, much like we put up with a knocking noise on the old car....

I am eternaly surprised by the bugs in Xilinx VHDL, it seems all thier design work is done in Verilog, so dont hold any breath ..

 

Well found,

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Observer nebenni
Observer
630 Views
Registered: ‎05-08-2018

Re: [BUG report] VHDL: type natural accepts negative values

This is why i like open source. If the company does not care, i can at least fix it myself.

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Highlighted
Scholar brimdavis
Scholar
577 Views
Registered: ‎04-26-2012

Re: [BUG report] VHDL: type natural accepts negative values

@nebenni  "vivado seems to ignore the range-constraint completely."

Xilinx's default settings for XSIM and ISIM chuck the VHDL LRM out the proverbial window and disable VHDL range checking (apparently so their marketeers can brag about simulation speed...)

Use -rangecheck on the command line,  or change the default in the Vivado GUI:

  Project Settings=>Simulation=>Simulation Settings Pane=>Elaboration tab=> xsim.elaborate.rangecheck

----------------------------------

Setting the WayBack machine to 2013 yields a typical customer complaint about this:

  https://forums.xilinx.com/t5/Simulation-and-Verification/Isim-natural-counter-exceeds-its-range/td-p/359383

Quoting @bassman59 's response to Xilinx employee @debrajr from this 2013 thread:

" It's the wrong default. Especially when the customers don't realize that such an option exists, and thus time is wasted trying to determine why the simulator doesn't do what the LRM specifies and the user expects."

By this point in time, Xilinx has wasted man-centuries of their customers' design time by refusing to fix this ridiculous default setting.

-Brian

Scholar richardhead
Scholar
552 Views
Registered: ‎08-01-2012

Re: [BUG report] VHDL: type natural accepts negative values

Wow. Xilinx just does the opposite of everyone else, which is LRM by default, switches for relaxing it.

Another reason to ditch the vivado simulator asap.

GHDL is free and open source.

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Moderator
Moderator
448 Views
Registered: ‎09-15-2016

Re: [BUG report] VHDL: type natural accepts negative values

Hi @nebenni ,

Thanks for reporting this issue. I have checked this test case at my end. I came across the below warning messages during the elaboration, and I agree that it should have errored out. Hence, I have filed a CR on this and reported it to the factory to get this issue fixed in future versions of the Vivado tool.

WARNING: [VRFC 10-1537] value -42 is out of target constraint range 0 to 255 [/proj/css/sravanthiB/project_vhdl_integer/project_vhdl_integer.srcs/sources_1/new/test.vhd:43]
WARNING: [VRFC 10-1537] value -1000 is out of target constraint range 0 to 2147483647 [/proj/css/sravanthiB/project_vhdl_integer/project_vhdl_integer.srcs/sources_1/new/test.vhd:48]

Thanks & Regards,
Sravanthi B
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Observer nebenni
Observer
436 Views
Registered: ‎05-08-2018

Re: [BUG report] VHDL: type natural accepts negative values

@banban 

Ok. I will accept this as a solution when the bug is fixed...

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Observer nebenni
Observer
426 Views
Registered: ‎05-08-2018

Re: [BUG report] VHDL: type natural accepts negative values

Hello @bandi ,

i checked again because i was sure i didnt see a message at all in my project:

In the minimal example, i get the warning (which should be a error).

In my real-life-project, i dont get any message, even if i enable the range check mentioned by @brimdavis (which should be on by default).

 

Interesting that there is a difference at all. I have noticed such "seemingly random behaviour" from time to time with vivado, where a seemingly unrelated change in the code changes the behaviour and detection of such errors. (had another one where a string variable was unconstrained, which worked fine in some cases and an not in other cases, despite it beeing the in the same unchanged function, just called a bit later in the main code.

Scholar brimdavis
Scholar
401 Views
Registered: ‎04-26-2012

Re: [BUG report] VHDL: type natural accepts negative values

@nebenni   " i dont get any message, even if i enable the range check"

What version/platform  of Vivado are you using ?

In 2018.3, with the xsim.elaborate.rangecheck flag set, I get the following error when running simulation:

ERROR: runtime range check value -1000 is out of valid range 0 to 2147483647

Along with the elaboration-time warnings (which IMHO should also be errors)

Starting static elaboration
WARNING: [VRFC 10-1537] value -42 is out of target constraint range 0 to 255 [D:/sandbox/vivado_test/range_check/hdl/range_check.vhd:26]
WARNING: [VRFC 10-1537] value -1000 is out of target constraint range 0 to 2147483647 [D:/sandbox/vivado_test/range_check/hdl/range_check.vhd:31]

EDIT(clarify): Even with range checking turned on, I see only one runtime error (from the assignment to -1000); this suggests that Xilinx has implemented runtime range checking for assignments but not for procedure parameters, since the first iterations are passing an illegal value to the procedure.

 

Observer nebenni
Observer
352 Views
Registered: ‎05-08-2018

Re: [BUG report] VHDL: type natural accepts negative values

Im using 2019.1 on Linux.

With xsim.elaborate.rangecheck enabled, i get the following output:

# run 1000ns
Note: called demoproc, numberOfCells is -3
Time: 50 ns  Iteration: 0  Process: /example/line__19  File: /home/myusername/bug_negative_range_0_to_positive/bug_negative_range_0_to_positive.srcs/sources_1/new/example.vhd
Note: called demoproc, numberOfCells is -2
Time: 150 ns  Iteration: 0  Process: /example/line__19  File: /home/myusername/bug_negative_range_0_to_positive/bug_negative_range_0_to_positive.srcs/sources_1/new/example.vhd
Note: called demoproc, numberOfCells is -1
Time: 250 ns  Iteration: 0  Process: /example/line__19  File: /home/myusername/bug_negative_range_0_to_positive/bug_negative_range_0_to_positive.srcs/sources_1/new/example.vhd
Note: called demoproc, numberOfCells is 0
Time: 350 ns  Iteration: 0  Process: /example/line__19  File: /home/myusername/bug_negative_range_0_to_positive/bug_negative_range_0_to_positive.srcs/sources_1/new/example.vhd
Note: called demoproc, numberOfCells is 1
Time: 450 ns  Iteration: 0  Process: /example/line__19  File: /home/myusername/bug_negative_range_0_to_positive/bug_negative_range_0_to_positive.srcs/sources_1/new/example.vhd
Note: called demoproc, numberOfCells is 2
Time: 550 ns  Iteration: 0  Process: /example/line__19  File: /home/myusername/bug_negative_range_0_to_positive/bug_negative_range_0_to_positive.srcs/sources_1/new/example.vhd
Note: called demoproc, numberOfCells is 3
Time: 650 ns  Iteration: 0  Process: /example/line__19  File: /home/myusername/bug_negative_range_0_to_positive/bug_negative_range_0_to_positive.srcs/sources_1/new/example.vhd
ERROR: runtime range check value -1000 is out of valid range 0 to 2147483647
Time: 750 ns  Iteration: 0  Process: /example/line__19
  File: /home/myusername/bug_negative_range_0_to_positive/bug_negative_range_0_to_positive.srcs/sources_1/new/example.vhd

HDL Line: /home/myusername/bug_negative_range_0_to_positive/bug_negative_range_0_to_positive.srcs/sources_1/new/example.vhd:31
INFO: [USF-XSim-96] XSim completed. Design snapshot 'example_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns

As mentioned in your edit, there is no message at all when calling the procedure with negative numbers (tested with rangecheck on and off).

@bandi So this is an additional bug, where the message does not occur at all.

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Observer nebenni
Observer
300 Views
Registered: ‎05-08-2018

Re: [BUG report] VHDL: type natural accepts negative values

@bandi Tested it with the new 2019.2 - same behaviour. No message at all for the procedure-call with negative numbers.

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Observer nebenni
Observer
296 Views
Registered: ‎05-08-2018

Re: [BUG report] VHDL: type natural accepts negative values

Another test:

procedure demoproc(constant numberOfCells : in natural range 0 to 255) is
	   variable var : natural range 0 to 255;
	begin
	   var := -300;
	   report "called demoproc, var is "&natural'IMAGE(var) severity note;
	   report "called demoproc, numberOfCells is "&natural'IMAGE(numberOfCells) severity note;
	   var := var + numberOfCells;
	   report "called demoproc, var is "&natural'IMAGE(var) severity note;
	end procedure;

Result: No messages at all - i am starting to think vivado doesnt do range checking in procedures at all...

Historian
Historian
90 Views
Registered: ‎02-25-2008

Re: [BUG report] VHDL: type natural accepts negative values

Holy crap, literally YEARS after pointing out that this sort of error is a serious problem, it's still not fixed.

Maybe Xilinx wants to make VHDL more Verilog-like by tossing out the checks that make VHDL what it is.

I agree with the person who suggested using ghld. The most-recent version, 0.37, works quite well.

----------------------------Yes, I do this for a living.
Historian
Historian
89 Views
Registered: ‎02-25-2008

Re: [BUG report] VHDL: type natural accepts negative values

Of course I mean "ghdl" and not "ghld," but this new forum software doesn't seem to let you edit posts.

----------------------------Yes, I do this for a living.
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