cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Anonymous
Not applicable
2,616 Views

Behavioral models for PLL and SERDES

Hello,

 

I have to simulate my XILINX FPGA project (VIVADO v2015.04) in CADENCE NCSIM (v15.20.008).

 

My idea is to port the FPGA RTL files and add some behavioral models (Verilog or VHDL) for the IPs I have used in the FPGA: IO buffers, SERDES and PLL. Are these behavioral models available, or do I need to do something different?

 

Thanks.

 

Bernardo

0 Kudos
3 Replies
Highlighted
Voyager
Voyager
2,581 Views
Registered: ‎06-24-2013

Hey @Anonymous,

 

Are these behavioral models available, or do I need to do something different?

Most of the Xilinx primitives are available in the unisim library and simulation libraries for 3rd party simulators can be built with compile_simlib. AR# 64083 has all the details.

 

Hope this helps,

Herbert

-------------- Yes, I do this for fun!
0 Kudos
Highlighted
Anonymous
Not applicable
2,564 Views

Hi hpoerzl,

 

actually I cannot find CADENCE SimVision as an option for compile_simlib. These are my options:

 

* modelsim - Version 10.4b and later

* questa - Version 10.4b and later

* ies - (Linux only) Version 14.20.006 or later

* vcs_mx - (Linux only) Version J-2014.12-SP2 or later

* riviera - Version 2015.02 or later

* active_hdl - (Windows only) Version 10.2

 

It should be vcs_mx (?) but anyhow it is an option for running under Linux linux, while I am running Vivado in Windows.

 

Is this precompiled library available somewhere?

 

 

0 Kudos
Highlighted
Voyager
Voyager
2,551 Views
Registered: ‎06-24-2013

Hey Bernardo,

 

Maybe those answer records can help:

AR# 58890 Third Party Simulators - Cadence IES

AR# 58891 Third Party Simulators - Synopsys VCS​/VCS-MX

 

Is this precompiled library available somewhere?

Not that I'd know of, but maybe there is ...

 

Best,

Herbert

-------------- Yes, I do this for fun!
0 Kudos