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6,824 Views
Registered: ‎03-27-2014

Behavioral simulation of a signed(a)*signed(b) operation

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Hi,

 

I am working on 7000 serie FPGAs (Zedboard, Zc706..), I like proposing multiple implementation choices for my IPs: performance/resource optimization etc..

The multiplier object on these FPGA is named DSP48E1 and can perform A[25]xB[18] in one clock cycle at up to 600MHz.

 

The thing is, If I simulate something like (Vivado 2014.4):

 

process( clk )
begin
[...]
     if tvalid_i = '1' then
         tvalid_o <= '1';
         result <= std_logic_vector( signed(a32) * signed(b32));
    end if;
[...]

this produces the expected behaviour, for whatever input frequency and (apparently..) whatever data size.

 

Could Xilinx experts confirm in this case the behavior is wrong and we should only refer to a post-implementation simulation? Or am I missing something on the DSP48E1 spec

 

thank you

G.W.,
NIST - Time Frequency metrology
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Professor
Professor
13,208 Views
Registered: ‎08-14-2007

Re: Behavioral simulation of a signed(a)*signed(b) operation

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For behavioral simulation, the simulator is not simulating DSP48E1 blocks.  It simply implements whatever you have coded in HDL.  However, once you synthesize and implement the design, the behavior should still match this simulation as long as you properly constrain timing and meet those constraints.  It will not be possible to run 600 MHz even at 18 by 25 bits unless you insert the appropriate number of pipeline stages in your HDL to use the internal registers of the DSP48E1.  The DSP48E1 runs considerably slower in non-pipelined (combinatorial) mode.

-- Gabor

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Professor
Professor
13,209 Views
Registered: ‎08-14-2007

Re: Behavioral simulation of a signed(a)*signed(b) operation

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For behavioral simulation, the simulator is not simulating DSP48E1 blocks.  It simply implements whatever you have coded in HDL.  However, once you synthesize and implement the design, the behavior should still match this simulation as long as you properly constrain timing and meet those constraints.  It will not be possible to run 600 MHz even at 18 by 25 bits unless you insert the appropriate number of pipeline stages in your HDL to use the internal registers of the DSP48E1.  The DSP48E1 runs considerably slower in non-pipelined (combinatorial) mode.

-- Gabor

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Teacher
Teacher
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Registered: ‎03-31-2012

Re: Behavioral simulation of a signed(a)*signed(b) operation

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RTL simulation is untimed so as you say, it would work for any data size and any frequency. You can make your clock period 1 picosecond and it would still work. You don't have to do post-implementation simulation but you have to implement and then time your design to see how fast it would run (or more usually, implement your design and check timing at a specific frequency you are interested to see if it would meet timing)
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