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phara0h
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Registered: ‎12-17-2017

Behavioral simulation works but post-synthesis and post-implementation do not

I switched from VHDL to SystemVerilog and have a problem with simulation. Behavioral simulation works and synthesis and implementation run without any errors/warnings. However I i run post-synthesis or post-implemenation I get

INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/ItLCaLDwVerilog_computer/ItLCaLDwVerilog_computer.srcs/sim_1/new/computer_tb.sv" into library xil_defaultlib
ERROR: [VRFC 10-2989] 'common' is not declared [/ItLCaLDwVerilog_computer/ItLCaLDwVerilog_computer.srcs/sim_1/new/computer_tb.sv:1]
INFO: [VRFC 10-311] analyzing module computer_tb
ERROR: [VRFC 10-2865] module 'computer_tb' ignored due to previous errors [/ItLCaLDwVerilog_computer/ItLCaLDwVerilog_computer.srcs/sim_1/new/computer_tb.sv:3]
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds

line computer_tb.sv:1:

import common::*;

 

common.sv contains a a package common is first in compile order. Any Ideas what causes the error and how to fix it?

 

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sunilku
Xilinx Employee
Xilinx Employee
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Registered: ‎08-10-2015

hi @phara0h ,

 

ERROR: [VRFC 10-2989] 'common' is not declared [/ItLCaLDwVerilog_computer/ItLCaLDwVerilog_computer.srcs/sim_1/new/computer_tb.sv, This error seen due to the variable used which is not defined in the design file. Please check if the signal common is exist in the file computer_tb.sv is exist or not.

Please share the design if you are still facing the issue.

 

Thanks,

Sunilkumar

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phara0h
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Registered: ‎12-17-2017

'common' is not a signal, it'a a package name:

in file computer_tb.sv

import common::*;

module computer_tb;

..

 

in common.sv:

package common;

..

 

After setting incremental to "Off" i get

 

ERROR: [VRFC 10-2991] 'romfile' is not declared under prefix 'rom0' [/home/pharaoh/Projekte/FPGA/ItLCaLDwVerilog_computer/ItLCaLDwVerilog_computer.srcs/sim_1/new/computer_tb.sv:7]
ERROR: [VRFC 10-2991] 'PC' is not declared under prefix 'data_path0' [/home/pharaoh/Projekte/FPGA/ItLCaLDwVerilog_computer/ItLCaLDwVerilog_computer.srcs/sim_1/new/computer_tb.sv:91]
ERROR: [VRFC 10-2991] 'IReg' is not declared under prefix 'data_path0' [/home/pharaoh/Projekte/FPGA/ItLCaLDwVerilog_computer/ItLCaLDwVerilog_computer.srcs/sim_1/new/computer_tb.sv:92]
ERROR: [VRFC 10-2991] 'MAReg' is not declared under prefix 'data_path0' [/home/pharaoh/Projekte/FPGA/ItLCaLDwVerilog_computer/ItLCaLDwVerilog_computer.srcs/sim_1/new/computer_tb.sv:93]
ERROR: [VRFC 10-2991] 'A' is not declared under prefix 'data_path0' [/home/pharaoh/Projekte/FPGA/ItLCaLDwVerilog_computer/ItLCaLDwVerilog_computer.srcs/sim_1/new/computer_tb.sv:94]
ERROR: [VRFC 10-2991] 'B' is not declared under prefix 'data_path0' [/home/pharaoh/Projekte/FPGA/ItLCaLDwVerilog_computer/ItLCaLDwVerilog_computer.srcs/sim_1/new/computer_tb.sv:95]
ERROR: [VRFC 10-2991] 'CCR_Result' is not declared under prefix 'data_path0' [/home/pharaoh/Projekte/FPGA/ItLCaLDwVerilog_computer/ItLCaLDwVerilog_computer.srcs/sim_1/new/computer_tb.sv:97]
ERROR: [VRFC 10-2991] 'to_memory' is not declared under prefix 'data_path0' [/home/pharaoh/Projekte/FPGA/ItLCaLDwVerilog_computer/ItLCaLDwVerilog_computer.srcs/sim_1/new/computer_tb.sv:99]
ERROR: [VRFC 10-2991] 'write' is not declared under prefix 'control_unit0' [/home/pharaoh/Projekte/FPGA/ItLCaLDwVerilog_computer/ItLCaLDwVerilog_computer.srcs/sim_1/new/computer_tb.sv:100]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds

 

while runnung "post-synthesis functional".

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sunilku
Xilinx Employee
Xilinx Employee
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Registered: ‎08-10-2015

hi @phara0h 

 

There are multiple changes needed to make the design work in post-synthesis simulation.

1. System Verilog package(common.sv) should be used for both synthesis and simulation. In the design common.sv is marked as only for synthesis, So when netlist is generated, package definition will be converted into netlist and tesbench won't be able to find the definition of package

2. ERROR: [VRFC 10-2991] 'romfile' is not declared under prefix 'rom0', You are changing the parameter value using defparam from the testbench. parameter defined in module will be elaborated from the top level before netlist generation and won't be visible in nelist. Behavioral simulation works for this and synthesis simulation will fail for this scenario.

3. ERROR: [VRFC 10-2991] 'PC' is not declared under prefix 'data_path0'. you are trying to access the signal using hierarchical reference from the module. Netlist will convert the name of internal signals while generating the netlist. you can add the attribute (*don't_touch="true"*) to the module and internal signals for not changing the names in generated netlist.

Ex: (*dont_touch="true"*)

module data_path ();

(*dont_touch="true"*)register_t PC;

endmodule

4. computer.sv is used as dut in the design, but top_zedboard.sv file is marked as top for synthesis. It is better practice to use the DUT file used for simulation marked as synthesis top.

5. There are multiple testbench files added in simulation sources and those are no where used in design.  If you are adding files to simulation sources, flow will add them to the generated .prj files and compile them also. It is better practice to add only the required files for the simulation.

 

With the above changes I am able to run the design with out any issues

 

Thanks,

Sunilkumar.

 

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phara0h
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Registered: ‎12-17-2017

Hello @sunilku,

thanks for looking into it. May I ask some follow-up questions because I cannot get it to work?

1. I checked common.sv and it's marked as used in synthesis and and simulation, I checked the uploaded archive too:

get_property USED_IN [get_files /tmp/ItLCaLDwVerilog_computer/ItLCaLDwVerilog_computer.srcs/sources_1/new/common.sv]
synthesis implementation simulation

Do I miss something here? common.sv is already set for sumulation too, isn't it?

 

3. I was able to fix the error messages for the internal signal PC, IReg, MAReg, etc. but module ports like 'write' are still not found.

module control_unit()

(*dont_touch="true"*) output logic write,

ERROR: [VRFC 10-2991] 'write' is not declared under prefix 'control_unit0' [/home/pharaoh/Projekte/FPGA/ItLCaLDwVerilog_computer/ItLCaLDwVerilog_computer.srcs/sim_1/new/computer_tb.sv:100]


Maybe you could upload your changed design, so i can check what i missed?

Best regards

 

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sunilku
Xilinx Employee
Xilinx Employee
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Registered: ‎08-10-2015

hi @phara0h 

 

Please change the attribute definition mentioned below

(*dont_touch="true"*)

module control_unit();

output logic write;

endmodule

 

Thanks,

Sunilkumar

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phara0h
Observer
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Registered: ‎12-17-2017

Hello @sunilku

your last hint did the trick, post-synthesis funtional simulation works now, thanks.

However, timing still has the old problem:

INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/pharaoh/Projekte/FPGA/ItLCaLDwVerilog_computer/ItLCaLDwVerilog_computer.srcs/sim_1/new/computer_tb.sv" into library xil_defaultlib
ERROR: [VRFC 10-2989] 'common' is not declared [/home/pharaoh/Projekte/FPGA/ItLCaLDwVerilog_computer/ItLCaLDwVerilog_computer.srcs/sim_1/new/computer_tb.sv:1]
INFO: [VRFC 10-311] analyzing module computer_tb
ERROR: [VRFC 10-2865] module 'computer_tb' ignored due to previous errors [/home/pharaoh/Projekte/FPGA/ItLCaLDwVerilog_computer/ItLCaLDwVerilog_computer.srcs/sim_1/new/computer_tb.sv:3]
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-99] Step results log file:'/home/pharaoh/Projekte/FPGA/ItLCaLDwVerilog_computer/ItLCaLDwVerilog_computer.sim/sim_1/synth/timing/xsim/xvlog.log'

common.sv is set to be used in simulation, synthesis, implementation, what else could cause this error?

Best regards

 

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