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5,051 Views
Registered: ‎04-26-2012

Behavioral vs. Post-Route simulation mismatch

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Hello, 

I trying to implement a system that consists of : ( ISE 12.4 and Ism)

- 2 combinational blocks that performs many mathematical operations and therefore use several DSP modules.

- One  FF used to transfer the information from one block to another ( it is a recursive algorithm).

When I perform a behavioral simulation everything goes well, but when I run the Post-Route simulation the results are wrong.

 

In order to find the bug I try to simulate just the two comb blocks in cascade (to emulate one iteration) , in this case the Behavioral and Post-Route simulations work both properly.

 

So the problem seems to appears when I add the FF to feedback the info from the output of the second comb block to the input of the first one. My main problems is that inputs of the comb blocks are ok in both the B and PAR sim but the blocks deliver a different output in the PAR sim (And the clk freq seems to be ok because the outputs look very stable)

 

In the complete process I just get one kind of warning repeated several times for diff signals  : Unable to preserve the ordering for port bus UB on block Combinational_BT using the data UB<1><17:0>.

 

I setted up just one timing constraint consernign the clk period and is met ok.

 

The only wierd thing (I can see) in my project is the fact that I am using buses that are Vectors of std_logic vectors. When I tried to performe the first PAR simulation I found that the tools only support Two dimensional arrays (the std_logic_vector2 type) so I changed the buses but only at the outputs. So, PAR sim is running but in internal buses I'm still using Vectors of std_logic_vector. May be this could be the bug ??

 

I've atached the outputs of Beheavioral (top image ) and PAR (below) simulations. The signals Xb, Ub and Db are the output of the first comb block. The signals Z, Xt, Ut and Dt are its inputs. Note that the inputs are the same in both images but the results are diff.

 

Sorry for my bad Engilsh and many thanks in advance !!

EROOOOOR.png
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1 Solution

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Historian
Historian
6,159 Views
Registered: ‎02-25-2008

Re: Behavioral vs. Post-Route simulation mismatch

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@franciscoaiglesias wrote:
With DSP I mean the embedded multipliers, because my comb blocks have a lot of them (like 27 ) and no clk !

NO.

----------------------------Yes, I do this for a living.
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4 Replies
Teacher rcingham
Teacher
5,037 Views
Registered: ‎09-09-2010

Re: Behavioral vs. Post-Route simulation mismatch

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Perhaps your clock speed is too fast for the depth of combinatorial logic that you have designed.

Try running your Post-Route simulation with a 10x slower clock.

Did you constrain the clock properly in the UCF? If so, did the Post-Rout Timing Analysis generate any timing failure messages?

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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5,033 Views
Registered: ‎04-26-2012

Re: Behavioral vs. Post-Route simulation mismatch

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Hi, thanks for the answer. But unfortunately I've already used a slower clock. And timing Analysis doesn't shown any failure.
I have another question, can a DSP work asynchronously ?
Thanks!!
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5,032 Views
Registered: ‎04-26-2012

Re: Behavioral vs. Post-Route simulation mismatch

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With DSP I mean the embedded multipliers, because my comb blocks have a lot of them (like 27 ) and no clk !
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Historian
Historian
6,160 Views
Registered: ‎02-25-2008

Re: Behavioral vs. Post-Route simulation mismatch

Jump to solution

@franciscoaiglesias wrote:
With DSP I mean the embedded multipliers, because my comb blocks have a lot of them (like 27 ) and no clk !

NO.

----------------------------Yes, I do this for a living.
0 Kudos