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203 Views
Registered: ‎12-14-2019

Black Box Warning when using component

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Hello together,

I'm quiet new to VHDL programming so excuse me if I understood something wrong. I created some basic code I wanted to simulate. Here the code of file 1:

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Hello_World is
    Port ( Inp1 : in STD_LOGIC;
           Inp2 : in STD_LOGIC;
           Outp : out STD_LOGIC);
end Hello_World;

architecture Hello_World_Arch of Hello_World is
begin
    Outp <= (Inp1 and Inp2);
end Hello_World_Arch;

File 2:

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Hello_World_TB is
end Hello_World_TB;

architecture Hello_World_TB_Arch of Hello_World_TB is
    component Hello_World_Comp
        Port ( Inp1 : in STD_LOGIC;
               Inp2 : in STD_LOGIC;
               Outp : out STD_LOGIC);
    end component;
    
    signal Inp1_Sig : STD_LOGIC;
    signal Inp2_Sig : STD_LOGIC;
    signal Outp_Sig : STD_LOGIC;
begin
uut: Hello_World_Comp PORT MAP (Inp1=>Inp1_Sig, Inp2=>Inp2_Sig, Outp=>Outp_Sig);
--uut: entity work.Hello_World(Hello_World_Arch) port map (I1=>I1, I2=>I2, Output=>Output);
process
begin
    Inp1_Sig <= '0';
    Inp2_Sig <= '0';
    wait for 100ns;
    Inp1_Sig <= '1';
    Inp2_Sig <= '1';
    wait;
end process;
end Hello_World_TB_Arch;

configuration Hello_World_TB_Config of Hello_World_TB is
    for Hello_World_TB_Arch
        for uut : Hello_World_Comp
            use entity work.Hello_World(Hello_World_Arch);
        end for;
    end for;
end Hello_World_TB_Config;

I create an component from an entity of another file. I always get the following warning:

Bildschirmfoto 2019-12-14 um 17.21.30.png

In my source editor it's clearly linked to the other file:

Bildschirmfoto 2019-12-14 um 17.22.07.png

Also the simulation isn't working, it's always not defined the output:

Bildschirmfoto 2019-12-14 um 17.23.03.png

When I now use direct instantiation of the entity as following, the error is gone and the simulation is working.

--uut: entity work.Hello_World(Hello_World_Arch) port map (I1=>I1, I2=>I2, Output=>Output);

What am I doing wrong with the component?

Thanks for your support!

Kind regards

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1 Solution

Accepted Solutions
Scholar richardhead
Scholar
170 Views
Registered: ‎08-01-2012

Re: Black Box Warning when using component

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You've named the component

Hello_World_Comp

But the entity is actually called "Hello_World"

The Component name must match the entity so the mapper knows which entity to map the component to. The component is like a prototype. And also not required - if you can, stick with direct instantiation because missing ports are a syntax error which takes seconds to find, whereas missmatches between component and entity wont be picked up until elaboration, which may take several minutes for a large design.

View solution in original post

2 Replies
Scholar richardhead
Scholar
171 Views
Registered: ‎08-01-2012

Re: Black Box Warning when using component

Jump to solution

You've named the component

Hello_World_Comp

But the entity is actually called "Hello_World"

The Component name must match the entity so the mapper knows which entity to map the component to. The component is like a prototype. And also not required - if you can, stick with direct instantiation because missing ports are a syntax error which takes seconds to find, whereas missmatches between component and entity wont be picked up until elaboration, which may take several minutes for a large design.

View solution in original post

125 Views
Registered: ‎12-14-2019

Re: Black Box Warning when using component

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Thanks for the fast support! Now it is working but I keep using direct instantiation because it makes the code clearer in my opinion.
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