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Newbie dipster
Newbie
539 Views
Registered: ‎02-28-2018

Block Diagram based design blows up during sim

Guys,

 

I have a design that is block diagram based and has a mix of Xilinx IP and my own RTL. It has been working fine - simulating, synthesizing, etc. Today I made changes to one Verilog RTL module within the design and the whole thing blew up. Here'a a copy/paste of the errors. Any help would be greatly appreciated:

 

INFO: [BD 41-1662] The design 'design_1.bd' is already validated. Therefore parameter propagation will not be re-run.
VHDL Output written to : C:/Users/dasgupta/Desktop/IIP/Code/parser_w_stream_control/parser_w_stream_control/parser_w_stream_control.srcs/sources_1/bd/design_1/synth/design_1.v
VHDL Output written to : C:/Users/dasgupta/Desktop/IIP/Code/parser_w_stream_control/parser_w_stream_control/parser_w_stream_control.srcs/sources_1/bd/design_1/sim/design_1.v
VHDL Output written to : C:/Users/dasgupta/Desktop/IIP/Code/parser_w_stream_control/parser_w_stream_control/parser_w_stream_control.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v
INFO: [IP_Flow 19-3500] Reset failed 'Synthesis' target for IP 'parser_0'.
ERROR: [IP_Flow 19-3505] IP Generation error: Failed to generate IP 'parser_0'. Failed to generate 'Verilog Synthesis Wrapper' outputs:
ERROR: [IP_Flow 19-98] Generation of the IP CORE failed.
Failed to generate IP 'parser_0'. Failed to generate 'Verilog Synthesis Wrapper' outputs:
ERROR: [BD 41-1030] Generation failed for the IP Integrator block parser_0
CRITICAL WARNING: [IP_Flow 19-664] Failed to create directory 'c:/Users/dasgupta/Desktop/IIP/Code/parser_w_stream_control/parser_w_stream_control/parser_w_stream_control.srcs/sources_1/bd/design_1/ipshared/0ab1/hdl' to copy 'c:/Xilinx/Vivado/2017.3/data/ip/xilinx/axis_infrastructure_v1_1/hdl/axis_infrastructure_v1_1_0.vh' to.
CRITICAL WARNING: [IP_Flow 19-664] Failed to create directory 'c:/Users/dasgupta/Desktop/IIP/Code/parser_w_stream_control/parser_w_stream_control/parser_w_stream_control.srcs/sources_1/bd/design_1/ipshared/0ab1/hdl' to copy 'c:/Xilinx/Vivado/2017.3/data/ip/xilinx/axis_infrastructure_v1_1/hdl/axis_infrastructure_v1_1_vl_rfs.v' to.
ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).
CRITICAL WARNING: [IP_Flow 19-664] Failed to create directory 'c:/Users/dasgupta/Desktop/IIP/Code/parser_w_stream_control/parser_w_stream_control/parser_w_stream_control.srcs/sources_1/bd/design_1/ipshared/e50b/hdl' to copy 'c:/Xilinx/Vivado/2017.3/data/ip/xilinx/blk_mem_gen_v8_4/hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd' to.
ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).
CRITICAL WARNING: [IP_Flow 19-664] Failed to create directory 'c:/Users/dasgupta/Desktop/IIP/Code/parser_w_stream_control/parser_w_stream_control/parser_w_stream_control.srcs/sources_1/bd/design_1/ipshared/0798/hdl' to copy 'c:/Xilinx/Vivado/2017.3/data/ip/xilinx/fifo_generator_v13_2/hdl/fifo_generator_v13_2_vhsyn_rfs.vhd' to.
ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).
CRITICAL WARNING: [IP_Flow 19-664] Failed to create directory 'c:/Users/dasgupta/Desktop/IIP/Code/parser_w_stream_control/parser_w_stream_control/parser_w_stream_control.srcs/sources_1/bd/design_1/ipshared/f1e5/hdl' to copy 'c:/Xilinx/Vivado/2017.3/data/ip/xilinx/axis_data_fifo_v1_1/hdl/axis_data_fifo_v1_1_vl_rfs.v' to.
ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).
ERROR: [IP_Flow 19-3505] IP Generation error: Failed to generate IP 'write_FIFO'. Failed to generate 'Verilog Synthesis' outputs:
ERROR: [IP_Flow 19-98] Generation of the IP CORE failed.
Failed to generate IP 'write_FIFO'. Failed to generate 'Verilog Synthesis' outputs:
ERROR: [BD 41-1030] Generation failed for the IP Integrator block write_FIFO
CRITICAL WARNING: [IP_Flow 19-664] Failed to create directory 'c:/Users/dasgupta/Desktop/IIP/Code/parser_w_stream_control/parser_w_stream_control/parser_w_stream_control.srcs/sources_1/bd/design_1/ipshared/0ab1/hdl' to copy 'c:/Xilinx/Vivado/2017.3/data/ip/xilinx/axis_infrastructure_v1_1/hdl/axis_infrastructure_v1_1_0.vh' to.
CRITICAL WARNING: [IP_Flow 19-664] Failed to create directory 'c:/Users/dasgupta/Desktop/IIP/Code/parser_w_stream_control/parser_w_stream_control/parser_w_stream_control.srcs/sources_1/bd/design_1/ipshared/0ab1/hdl' to copy 'c:/Xilinx/Vivado/2017.3/data/ip/xilinx/axis_infrastructure_v1_1/hdl/axis_infrastructure_v1_1_vl_rfs.v' to.
ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).
CRITICAL WARNING: [IP_Flow 19-664] Failed to create directory 'c:/Users/dasgupta/Desktop/IIP/Code/parser_w_stream_control/parser_w_stream_control/parser_w_stream_control.srcs/sources_1/bd/design_1/ipshared/e50b/hdl' to copy 'c:/Xilinx/Vivado/2017.3/data/ip/xilinx/blk_mem_gen_v8_4/hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd' to.
ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).
CRITICAL WARNING: [IP_Flow 19-664] Failed to create directory 'c:/Users/dasgupta/Desktop/IIP/Code/parser_w_stream_control/parser_w_stream_control/parser_w_stream_control.srcs/sources_1/bd/design_1/ipshared/0798/hdl' to copy 'c:/Xilinx/Vivado/2017.3/data/ip/xilinx/fifo_generator_v13_2/hdl/fifo_generator_v13_2_vhsyn_rfs.vhd' to.
ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).
CRITICAL WARNING: [IP_Flow 19-664] Failed to create directory 'c:/Users/dasgupta/Desktop/IIP/Code/parser_w_stream_control/parser_w_stream_control/parser_w_stream_control.srcs/sources_1/bd/design_1/ipshared/f1e5/hdl' to copy 'c:/Xilinx/Vivado/2017.3/data/ip/xilinx/axis_data_fifo_v1_1/hdl/axis_data_fifo_v1_1_vl_rfs.v' to.
ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).
ERROR: [IP_Flow 19-3505] IP Generation error: Failed to generate IP 'read_FIFO'. Failed to generate 'Verilog Synthesis' outputs:
ERROR: [IP_Flow 19-98] Generation of the IP CORE failed.
Failed to generate IP 'read_FIFO'. Failed to generate 'Verilog Synthesis' outputs:
ERROR: [BD 41-1030] Generation failed for the IP Integrator block read_FIFO
INFO: [IP_Flow 19-3500] Reset failed 'Simulation' target for IP 'stream_control_0'.
ERROR: [IP_Flow 19-3505] IP Generation error: Failed to generate IP 'stream_control_0'. Failed to generate 'Verilog Simulation Wrapper' outputs:
ERROR: [IP_Flow 19-98] Generation of the IP CORE failed.
Failed to generate IP 'stream_control_0'. Failed to generate 'Verilog Simulation Wrapper' outputs:
ERROR: [BD 41-1030] Generation failed for the IP Integrator block stream_control_0
CRITICAL WARNING: [IP_Flow 19-664] Failed to create directory 'c:/Users/dasgupta/Desktop/IIP/Code/parser_w_stream_control/parser_w_stream_control/parser_w_stream_control.srcs/sources_1/bd/design_1/ipshared/d46a/hdl' to copy 'c:/Xilinx/Vivado/2017.3/data/ip/xilinx/dist_mem_gen_v8_0/hdl/dist_mem_gen_v8_0_vhsyn_rfs.vhd' to.
ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).
CRITICAL WARNING: [IP_Flow 19-664] Failed to create directory 'c:/Users/dasgupta/Desktop/IIP/Code/parser_w_stream_control/parser_w_stream_control/parser_w_stream_control.srcs/sources_1/bd/design_1/ipshared/e50b/hdl' to copy 'c:/Xilinx/Vivado/2017.3/data/ip/xilinx/blk_mem_gen_v8_4/hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd' to.
ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).
CRITICAL WARNING: [IP_Flow 19-664] Failed to create directory 'c:/Users/dasgupta/Desktop/IIP/Code/parser_w_stream_control/parser_w_stream_control/parser_w_stream_control.srcs/sources_1/bd/design_1/ipshared/8679/hdl' to copy 'c:/Xilinx/Vivado/2017.3/data/ip/xilinx/lib_bmg_v1_0/hdl/lib_bmg_v1_0_rfs.vhd' to.
ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).
CRITICAL WARNING: [IP_Flow 19-664] Failed to create directory 'c:/Users/dasgupta/Desktop/IIP/Code/parser_w_stream_control/parser_w_stream_control/parser_w_stream_control.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl' to copy 'c:/Xilinx/Vivado/2017.3/data/ip/xilinx/lib_cdc_v1_0/hdl/lib_cdc_v1_0_rfs.vhd' to.
ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).
ERROR: [Ipptcl 7-5] XIT evaluation error: CRITICAL WARNING: [IP_Flow 19-664] Failed to create directory 'c:/Users/dasgupta/Desktop/IIP/Code/parser_w_stream_control/parser_w_stream_control/parser_w_stream_control.srcs/sources_1/bd/design_1/ip/design_1_axi_traffic_gen_0_0/netlist' to copy 'c:/Xilinx/Vivado/2017.3/data/ip/xilinx/axi_traffic_gen_v3_0/netlist/default_prm.coe' to.

ERROR: [Common 17-39] 'xit::copy_ipfile' failed due to earlier errors.
CRITICAL WARNING: [IP_Flow 19-1747] Failed to deliver file 'c:/Xilinx/Vivado/2017.3/data/ip/xilinx/axi_traffic_gen_v3_0/hdl/src/verilog/mem_init_default_prm.xit': ERROR: [Common 17-39] 'xit::copy_ipfile' failed due to earlier errors.

ERROR: [Ipptcl 7-5] XIT evaluation error: CRITICAL WARNING: [IP_Flow 19-664] Failed to create directory 'c:/Users/dasgupta/Desktop/IIP/Code/parser_w_stream_control/parser_w_stream_control/parser_w_stream_control.srcs/sources_1/bd/design_1/ip/design_1_axi_traffic_gen_0_0/netlist' to copy 'c:/Xilinx/Vivado/2017.3/data/ip/xilinx/axi_traffic_gen_v3_0/netlist/default_adr.coe' to.

ERROR: [Common 17-39] 'xit::copy_ipfile' failed due to earlier errors.
CRITICAL WARNING: [IP_Flow 19-1747] Failed to deliver file 'c:/Xilinx/Vivado/2017.3/data/ip/xilinx/axi_traffic_gen_v3_0/hdl/src/verilog/mem_init_default_adr.xit': ERROR: [Common 17-39] 'xit::copy_ipfile' failed due to earlier errors.

ERROR: [Ipptcl 7-5] XIT evaluation error: CRITICAL WARNING: [IP_Flow 19-664] Failed to create directory 'c:/Users/dasgupta/Desktop/IIP/Code/parser_w_stream_control/parser_w_stream_control/parser_w_stream_control.srcs/sources_1/bd/design_1/ip/design_1_axi_traffic_gen_0_0/netlist' to copy 'c:/Xilinx/Vivado/2017.3/data/ip/xilinx/axi_traffic_gen_v3_0/netlist/default_mst.coe' to.

ERROR: [Common 17-39] 'xit::copy_ipfile' failed due to earlier errors.
CRITICAL WARNING: [IP_Flow 19-1747] Failed to deliver file 'c:/Xilinx/Vivado/2017.3/data/ip/xilinx/axi_traffic_gen_v3_0/hdl/src/verilog/mem_init_default_mst.xit': ERROR: [Common 17-39] 'xit::copy_ipfile' failed due to earlier errors.

ERROR: [Ipptcl 7-5] XIT evaluation error: CRITICAL WARNING: [IP_Flow 19-664] Failed to create directory 'c:/Users/dasgupta/Desktop/IIP/Code/parser_w_stream_control/parser_w_stream_control/parser_w_stream_control.srcs/sources_1/bd/design_1/ip/design_1_axi_traffic_gen_0_0/netlist' to copy 'c:/Xilinx/Vivado/2017.3/data/ip/xilinx/axi_traffic_gen_v3_0/netlist/default_cmd.coe' to.

ERROR: [Common 17-39] 'xit::copy_ipfile' failed due to earlier errors.
CRITICAL WARNING: [IP_Flow 19-1747] Failed to deliver file 'c:/Xilinx/Vivado/2017.3/data/ip/xilinx/axi_traffic_gen_v3_0/hdl/src/verilog/mem_init_default_cmd.xit': ERROR: [Common 17-39] 'xit::copy_ipfile' failed due to earlier errors.

CRITICAL WARNING: [IP_Flow 19-664] Failed to create directory 'c:/Users/dasgupta/Desktop/IIP/Code/parser_w_stream_control/parser_w_stream_control/parser_w_stream_control.srcs/sources_1/bd/design_1/ipshared/a890/hdl/src/verilog' to copy 'c:/Xilinx/Vivado/2017.3/data/ip/xilinx/axi_traffic_gen_v3_0/hdl/src/verilog/axi_traffic_gen_v3_0_0_defines.v' to.
ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).
ERROR: [IP_Flow 19-3505] IP Generation error: Failed to generate IP 'axi_traffic_gen_0'. Failed to generate 'Synthesis' outputs:
ERROR: [IP_Flow 19-98] Generation of the IP CORE failed.
Failed to generate IP 'axi_traffic_gen_0'. Failed to generate 'Synthesis' outputs:
ERROR: [BD 41-1030] Generation failed for the IP Integrator block axi_traffic_gen_0
CRITICAL WARNING: [IP_Flow 19-664] Failed to create directory 'c:/Users/dasgupta/Desktop/IIP/Code/parser_w_stream_control/parser_w_stream_control/parser_w_stream_control.srcs/sources_1/bd/design_1/ipshared/0750/hdl' to copy 'c:/Xilinx/Vivado/2017.3/data/ip/xilinx/xlconstant_v1_1/hdl/xlconstant_v1_1_vl_rfs.v' to.
ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).
ERROR: [IP_Flow 19-3505] IP Generation error: Failed to generate IP 'xlconstant_0'. Failed to generate 'Verilog Synthesis' outputs:
ERROR: [IP_Flow 19-98] Generation of the IP CORE failed.
Failed to generate IP 'xlconstant_0'. Failed to generate 'Verilog Synthesis' outputs:
ERROR: [BD 41-1030] Generation failed for the IP Integrator block xlconstant_0
CRITICAL WARNING: [IP_Flow 19-664] Failed to create directory 'c:/Users/dasgupta/Desktop/IIP/Code/parser_w_stream_control/parser_w_stream_control/parser_w_stream_control.srcs/sources_1/bd/design_1/ipshared/0750/hdl' to copy 'c:/Xilinx/Vivado/2017.3/data/ip/xilinx/xlconstant_v1_1/hdl/xlconstant_v1_1_vl_rfs.v' to.
ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).
ERROR: [IP_Flow 19-3505] IP Generation error: Failed to generate IP 'xlconstant_1'. Failed to generate 'Verilog Synthesis' outputs:
ERROR: [IP_Flow 19-98] Generation of the IP CORE failed.
Failed to generate IP 'xlconstant_1'. Failed to generate 'Verilog Synthesis' outputs:
ERROR: [BD 41-1030] Generation failed for the IP Integrator block xlconstant_1
INFO: [IP_Flow 19-3500] Reset failed 'Synthesis' target for IP 'smartconnect_0'.
ERROR: [IP_Flow 19-3505] IP Generation error: Failed to generate IP 'smartconnect_0'. Failed to generate 'Verilog Synthesis Wrapper' outputs:
ERROR: [IP_Flow 19-98] Generation of the IP CORE failed.
Failed to generate IP 'smartconnect_0'. Failed to generate 'Verilog Synthesis Wrapper' outputs:
ERROR: [BD 41-1030] Generation failed for the IP Integrator block smartconnect_0
CRITICAL WARNING: [IP_Flow 19-664] Failed to create directory 'c:/Users/dasgupta/Desktop/IIP/Code/parser_w_stream_control/parser_w_stream_control/parser_w_stream_control.srcs/sources_1/bd/design_1/ipshared/ec67/hdl' to copy 'c:/Xilinx/Vivado/2017.3/data/ip/xilinx/axi_infrastructure_v1_1/hdl/axi_infrastructure_v1_1_0.vh' to.
CRITICAL WARNING: [IP_Flow 19-664] Failed to create directory 'c:/Users/dasgupta/Desktop/IIP/Code/parser_w_stream_control/parser_w_stream_control/parser_w_stream_control.srcs/sources_1/bd/design_1/ipshared/ec67/hdl' to copy 'c:/Xilinx/Vivado/2017.3/data/ip/xilinx/axi_infrastructure_v1_1/hdl/axi_infrastructure_v1_1_vl_rfs.v' to.
ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).
CRITICAL WARNING: [IP_Flow 19-664] Failed to create directory 'c:/Users/dasgupta/Desktop/IIP/Code/parser_w_stream_control/parser_w_stream_control/parser_w_stream_control.srcs/sources_1/bd/design_1/ipshared/8b42/hdl' to copy 'c:/Xilinx/Vivado/2017.3/data/ip/xilinx/axi_vip_v1_1/hdl/axi_vip_v1_1_vlsyn_rfs.sv' to.
ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).
ERROR: [IP_Flow 19-3505] IP Generation error: Failed to generate IP 'axi_vip_0'. Failed to generate 'Verilog Synthesis' outputs:
ERROR: [IP_Flow 19-98] Generation of the IP CORE failed.
Failed to generate IP 'axi_vip_0'. Failed to generate 'Verilog Synthesis' outputs:
ERROR: [BD 41-1030] Generation failed for the IP Integrator block axi_vip_0
CRITICAL WARNING: [IP_Flow 19-664] Failed to create directory 'c:/Users/dasgupta/Desktop/IIP/Code/parser_w_stream_control/parser_w_stream_control/parser_w_stream_control.srcs/sources_1/bd/design_1/ipshared/0750/hdl' to copy 'c:/Xilinx/Vivado/2017.3/data/ip/xilinx/xlconstant_v1_1/hdl/xlconstant_v1_1_vl_rfs.v' to.
ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).
ERROR: [IP_Flow 19-3505] IP Generation error: Failed to generate IP 'xlconstant_2'. Failed to generate 'Verilog Synthesis' outputs:
ERROR: [IP_Flow 19-98] Generation of the IP CORE failed.
Failed to generate IP 'xlconstant_2'. Failed to generate 'Verilog Synthesis' outputs:
ERROR: [BD 41-1030] Generation failed for the IP Integrator block xlconstant_2
ERROR: unknown error occurred

 

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Scholar hbucher
Scholar
535 Views
Registered: ‎03-22-2016

Re: Block Diagram based design blows up during sim

@dipster Just a hunch, it looks like a permission issue. It says failed to create directory. Make sure you have write access to all folders in the project. 

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